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82c836 chipset single-chip 386sx at data sheet march 1993 preliminary a
copyright notice software copyright ? 1993, chips and technologies, inc. manual copyright ? 1993, chips and technologies, inc. all rights reserved. printed in u.s.a. trademark acknowledgment chips a and chips logotype are registered trademarks of chips and technologies, inc. neat ? , neatsx ? , scat ? , and scatsx ? are trademarks of chips and technologies, inc. ibm a , ibm pc a , ibm pc/at a , ps2 ? , and microchannel ? are trademarks of intermational business machines corporation. intel a , 386 ? , 387 ? , are trademarks of intel corporation. lotus a is a registered trademark of lotus development corporation. ms-dos a is a registered trademark of microsoft corporation. motorola a is a registered trademark of motorola. disclaimer this manual is copyrighted by chips and technologies, inc. you may not reproduce, transmit, transcr ibe, store in a retrieval system, or translate into any language or computer language, in any form or by any means , electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without express written permission of chips and technologies, inc. the information contained in this document is being issued in advance of the production cycle for th e device(s). the parameters for the device(s) may change before final production. chips and technologies, inc. makes no representations or warranties regarding the contents of this m anual. we reserve the right to revise the manual or make changes in the specifications of the product describe d within it at any time without notice and without obligation to notify any person of such revision or changes. the information contained in this manual is provided for general use by our customers. our customer s should be aware that the personal computer field is the subject of many patents. our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. it is the policy of chips and technologies, inc. to respect the valid patent rights of third parties and not to infringe upon or a ssist others to infringe upon such rights. restricted rights and limitations use, duplication, or disclosure by the government is subject to restrictions set forth in subparagra ph (c)(1)(ii) of the rights in technical data and computer software clause at 252.277-7013 chips and technologies, inc. 2950 zanker road san jose, california 95134 phone: 408-434-0600
contents section 1 82c836 chipset introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 section 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 signal pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 section 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 reset strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 battery backup and power-up/down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 standby power management and laptop support . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 operational power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 section 4 clock/bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 system reset and clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 bus control arbitration and basic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 section 5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 rom/shadow ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 dram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 scatsx memory address mapping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 scatsx memory bank utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 automatic memory configuration detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 support for external cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 expanded/extended memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 numeric coprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 keyboard controller interface ---- external 8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 chips and technologies, inc. p r e l i m i n a r y revision 3.0 v
section 6 real time clock and interval timer registers . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 real time clock interface ---- mc146818 compatible . . . . . . . . . . . . . . . . . . . . . . 6-1 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 real time clock address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 update cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 programmable interval timer ---- 8254 compatible . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 counter description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 programming the counter timer controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 read/write counter command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 latch counter command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 read-back command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 gate2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 section 7 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 controller operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 end-of-interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 fixed priority mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 specific rotation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 automatic rotation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 programming the interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 initialization command words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 operational command words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 section 8 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 dma operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 idle condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 program condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 active condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 auto-initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 dreq priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 compressed timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 n contents 82c836 chipset data sheet vi revision 3.0 p r e l i m i n a r y chips and technologies, inc.
dma register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 current address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 current word count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 base word count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 request mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 temporary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 special commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 section 9 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 i/o address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 section 10 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 ems page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 section 11 system timing relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 cpu access to at-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 -memcs16 and -iocs16 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 iochrdy and ows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 -na/-stcyc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 -cas only dram access by cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 local dram bank switch (sra mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 maximum wait state page miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 cache mode write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 early ready and lba modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 coprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 drq/dack scanning in mra mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 master arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 dma and master access to local memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 memory refresh (hlda and 14mhz-based) . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 hidden refresh (procclk-based, no hlda) . . . . . . . . . . . . . . . . . . . . . . . . 11-30 standby refresh (32khz-based) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 power turn-on and system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 82c836 chipset data sheet contents n chips and technologies, inc. p r e l i m i n a r y revision 3.0 vii
section 12 system characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 physical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 ac characteristics 16- and 20mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 cpu to local memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 cpu access to at-bus, on-board i/o, and rom . . . . . . . . . . . . . . . . . . . . . . 12-6 dma access to at-bus, on-board i/o, and rom . . . . . . . . . . . . . . . . . . . . . . 12-8 dma and at-bus master access to local memory . . . . . . . . . . . . . . . . . . . . . 12-9 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 miscellaneous parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 local bus access and cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 standy refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 ac characteristics 25mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 cpu to local memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 cpu to at-bus, on-board i/o, and rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 dma to at-bus, on-board i/o, and rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 dma and at-bus master access to local memory . . . . . . . . . . . . . . . . . . . . . 12-19 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 miscellaneous parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 local bus access and cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 standby refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 section 13 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 section 14 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 appendix a differences between 82c836a and 82c836b . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 n contents 82c836 chipset data sheet viii revision 3.0 p r e l i m i n a r y chips and technologies, inc.
list of figures 82c836 chipset introduction figure 1-1. scatsx basic system architecture . . . . . . . . . . . . . . . . . . . . . . . 1-2 pin assignments figure 2-1. 160-pin pfp pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 functional description figure 3-1. pull-low function ---- alternate implementation . . . . . . . . . . . . . . 3-2 figure 3-2. ps diode for external real time clock systems . . . . . . . . . . . . . 3-3 figure 3-3. battery backup circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 clock/bus control figure 4-1. clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 system interface figure 5-1. mra mode implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 figure 5-2. encoded ras generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-3. example of ems/extended memory . . . . . . . . . . . . . . . . . . . . . . . 5-15 figure 5-4. -readyo interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 figure 5-5. keyboard controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 figure 6-1. register a ---- address 0ah (all bits except uip are read/write) 6-4 figure 6-2. register b ---- address 0bh (read only) . . . . . . . . . . . . . . . . . . . . 6-5 figure 6-3. register c ---- address 0ch (read only) . . . . . . . . . . . . . . . . . . . . 6-6 figure 6-4. register d ---- address 0dh (read only) . . . . . . . . . . . . . . . . . . . . 6-7 figure 6-5. update cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 figure 6-6. programmable timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 figure 6-7. control word ---- address 043h . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 figure 6-8. read-back command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 figure 6-9. status byte command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 interrupt controller figure 7-1. cascaded interrupt controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 figure 7-2. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . 7-3 figure 7-3. initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 figure 7-4. fixed priority mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 figure 7-5. specific rotation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 figure 7-6. automatic rotation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 figure 7-7. icw1 ---- address 020h (0a0h) write only . . . . . . . . . . . . . . . . . 7-9 figure 7-8. icw2 ---- address 021h (0a1h) write only . . . . . . . . . . . . . . . . . 7-10 figure 7-9. icw3 format for intc1 ---- address 021h write only . . . . . . . . . 7-10 figure 7-10. icw3 format for intc2 ---- address 0a1h write only . . . . . . . . 7-10 figure 7-11. icw4 ---- address 021h (0a1h) write only . . . . . . . . . . . . . . . . . 7-11 figure 7-12. ocw ---- address 021h (0a1h) read/write . . . . . . . . . . . . . . . . . 7-12 figure 7-13. ocw2 ---- address 020h (0a0h) write only . . . . . . . . . . . . . . . . 7-13 figure 7-14. ocw3 ---- address 020h (0a0h) write only . . . . . . . . . . . . . . . . 7-14 dma controller figure 8-1. cascaded dma controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 figure 8-2. command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 figure 8-3. mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 figure 8-4. request register (write operaton) . . . . . . . . . . . . . . . . . . . . . . . . 8-12 82c836 chipset data sheet contents n chips and technologies, inc. p r e l i m i n a r y revision 3.0 ix
figure 8-5. request register read format . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 figure 8-6. request mask register ---- write single mask bit . . . . . . . . . . . . . 8-13 figure 8-7. request mask register ---- write all mask bits . . . . . . . . . . . . . . . 8-14 figure 8-8. status register (read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 system timing relationships figure 11-1. cpu access to at-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 figure 11-2. -memcs16 and -iocs16 timing . . . . . . . . . . . . . . . . . . . . . . . . 11-3 figure 11-3. -na/-stcyc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 figure 11-4. -memcs16 and -iocs16 timing . . . . . . . . . . . . . . . . . . . . . . . . 11-7 figure 11-5. iochrdy and -0ws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 figure 11-6. -cas-only dram access by cpu . . . . . . . . . . . . . . . . . . . . . . . 11-11 figure 11-7. local dram bank switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 figure 11-8. maximum wait state page miss . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 figure 11-9. cache mode write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 figure 11-10. early ready and -lba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 figure 11-11. coprocessor timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 figure 11-12. dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 figure 11-13. dma and master access to local memory . . . . . . . . . . . . . . . . . 11-23 figure 11-14. drq/dack scanning in mra mode . . . . . . . . . . . . . . . . . . . . . 11-25 figure 11-15. master arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 figure 11-16. refresh timing (hlda/14mhz-based) . . . . . . . . . . . . . . . . . . . 11-29 figure 11-17. hidden refresh (procclk-based, no hlda) . . . . . . . . . . . . . 11-31 figure 11-18. standby refresh (32khz-based) . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 figure 11-19. power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 timing diagrams figure 13-1. timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 figure 13-2. cpu to local memory ---- output responses and input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 figure 13-3. cpu at-bus, on-board i/o and rom ---- output responses . . . 13-3 figure 13-4. cpu to at-bus, on-board i/o and rom ---- input requirements 13-4 figure 13-5. dma to at-bus, on-board i/o, and rom ---- output responses 13-5 figure 13-6. dma to at-bus, on-board i/o and rom ---- input requirements 13-6 figure 13-7. dma and at-bus master access to local memory ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 figure 13-8. dma and at-bus master access to local memory ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 figure 13-9. refresh ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 figure 13-10. refresh ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 figure 13-11. miscellaneous parameters ---- output responses . . . . . . . . . . . . . . 13-9 figure 13-12. miscellaneous parameters ---- input requirements . . . . . . . . . . . . . 13-10 figure 13-13. local bus access and cache ---- output responses . . . . . . . . . . . . 13-10 figure 13-14. local bus access and cache ---- input requirements . . . . . . . . . . 13-11 figure 13-15. standby refresh ---- output responses . . . . . . . . . . . . . . . . . . . . . . 13-11 mechanical specifications figure 14-1. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 n contents 82c836 chipset data sheet x revision 3.0 p r e l i m i n a r y chips and technologies, inc.
list of tables 82c836 chipset introduction table 1-1. address and data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 table 1-2. bus ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 pin assignments table 2-1. clock input and output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 table 2-2. local bus interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-3. numeric coprocessor interface signals . . . . . . . . . . . . . . . . . . . . 2-5 table 2-4. memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 table 2-5. i/o channel interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-6. miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-7. alphabetical pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 table 2-8. numerical pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 functional description table 3-1. pins for strap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 clock/bus control table 4-1. scatsx cycle types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 system interface table 5-1. valid configurations ---- nonencoded or encoded ras . . . . . . . . . 5-6 table 5-2. valid configurations ---- encoded ras only . . . . . . . . . . . . . . . . . 5-7 table 5-3. 4mb dram configurations ---- nonencoded ras only . . . . . . . . 5-7 table 5-4. memory address mapping modes . . . . . . . . . . . . . . . . . . . . . . . . 5-9 table 5-5. memory configuration address ranges and interleaving sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 table 5-6. memory configuration address ranges and interleaving sequences encoded ras only . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-7. memory configuration address ranges and interleaving sequences nonencoded ras only . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 6-1. address map for the real time clock . . . . . . . . . . . . . . . . . . . . . 6-2 table 6-2. format for clock, calendar, and alarm data . . . . . . . . . . . . . . . . 6-3 table 6-3. counter timer control i/o addresses . . . . . . . . . . . . . . . . . . . . . . 6-11 table 6-4. gate pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 interrupt controller table 7-1. interrupt levels for system board . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 table 7-2. interrupt vector format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 dma controller table 8-1. dma request levels for each i/o channel . . . . . . . . . . . . . . . . . 8-2 address maps table 9-1. dma controller i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 table 9-2. interrupt controller i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-3. internal configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 table 9-4. index registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-5. timer counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 table 9-6. miscellaneous i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 82c836 chipset data sheet contents n chips and technologies, inc. p r e l i m i n a r y revision 3.0 xi
table 9-7. dma page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 table 9-8. interrupt controller ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 table 9-9. dma controller ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table 9-10. coprocessor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table 9-11. ems page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 table 9-12. memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 configuration registers table 10-1. index 01h ---- dma wait state control . . . . . . . . . . . . . . . . . . . . . 10-1 table 10-2. index 40h ---- 82c836 version, read only . . . . . . . . . . . . . . . . . . 10-2 table 10-3. index 41h ---- channel environment . . . . . . . . . . . . . . . . . . . . . . . 10-2 table 10-4. index 44h ---- peripheral control . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 table 10-5. index 45h ---- miscellaneous status, read only . . . . . . . . . . . . . . 10-4 table 10-6. index 46h ---- power management . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 table 10-7. index 48h ---- rom enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 table 10-8. index 49h ---- ram write protect . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-9. index 4ah ---- shadow ram enable 1 . . . . . . . . . . . . . . . . . . . . . 10-7 table 10-10. index 4bh ---- shadow ram enable 2 . . . . . . . . . . . . . . . . . . . . . . 10-8 table 10-11. index 4ch ---- shadow ram enable 3 . . . . . . . . . . . . . . . . . . . . . . 10-8 table 10-12. index 4dh ---- dram configuration . . . . . . . . . . . . . . . . . . . . . . . 10-9 table 10-13. index 4eh ---- extended memory boundary . . . . . . . . . . . . . . . . . 10-9 table 10-14. index 4fh ---- ems control register . . . . . . . . . . . . . . . . . . . . . . . 10-10 table 10-15. index 60h ---- laptop features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 table 10-16. index 61h ---- fast video control . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 table 10-17. index 62h ---- fast video ram enable . . . . . . . . . . . . . . . . . . . . . 10-13 table 10-18. index 63h ---- high performance refresh . . . . . . . . . . . . . . . . . . . 10-13 table 10-19. index 64h ---- cas timing for dma/master . . . . . . . . . . . . . . . . 10-15 table 10-20. port 208h ---- target page address . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 table 10-21. port 209h ---- page enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 table 10-22. port 20ah ---- ems page select . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 table 10-23. port 61h ---- control port/status . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 table 10-24. port 70h ---- rtc/cmos index and nmi mask . . . . . . . . . . . . . . 10-19 table 10-25. port 71h ---- rtc/cmos data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 table 10-26. port 92h ---- system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 system timing relationships table 11-1. delays from ale to start command in busclk cycles . . . . . 11-3 table 11-2. procclk cycles and hidden refresh . . . . . . . . . . . . . . . . . . . . 11-32 system characteristics table 12-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 table 12-2. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 table 12-3. capacitive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 table 12-4. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 table 12-5. dram parameter specifications . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 table 12-6. cpu to local memory ---- output responses . . . . . . . . . . . . . . . . 12-4 table 12-7. cpu to local memory ---- formula specifications . . . . . . . . . . . . 12-5 table 12-8. cpu to local memory ---- input requirements . . . . . . . . . . . . . . . 12-5 table 12-9. cpu to at-bus, on-board i/o, and rom ---- output responses . 12-6 table 12-10. cpu to at-bus, on-board i/o, and rom ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 table 12-11. cpu to at-bus, on-board i/o, and rom ---- input requirements 12-7 n contents 82c836 chipset data sheet xii revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-12. dma to at-bus, on-board i/o, and rom ---- output responses . 12-8 table 12-13. dma to at-bus, on-board i/o, and rom ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 table 12-14. dma to at-bus, on-board i/o, and rom ---- input requirements 12-9 table 12-15. dma and at-bus master access to local memory ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 table 12-16. dma and at-bus master access to local memory ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 table 12-17. dma and at-bus master access to local memory ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 table 12-18. refresh ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 table 12-19. refresh ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 table 12-20. refresh ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 table 12-21. miscellaneous parameters ---- output responses . . . . . . . . . . . . . . 12-12 table 12-22. miscellaneous parameters ---- formula specifications . . . . . . . . . . 12-12 table 12-23. miscellaneous parameters ---- input requirements . . . . . . . . . . . . . 12-12 table 12-24. local bus access and cache ---- output responses . . . . . . . . . . . . 12-13 table 12-25. local bus access and cache ---- formula specifications . . . . . . . . 12-13 table 12-26. local bus access and cache ---- input requirements . . . . . . . . . . . 12-13 table 12-27. standby refreshoutput responses . . . . . . . . . . . . . . . . . . . . . . . . 12-14 table 12-28. cpu to local memory ---- output responses . . . . . . . . . . . . . . . . . 12-15 table 12-29. cpu to local memory ---- formula specifications . . . . . . . . . . . . . 12-15 table 12-30. cpu to local memory ---- input requirements . . . . . . . . . . . . . . . . 12-16 table 12-31. cpu to at-bus, on-board i/o, and rom ---- output responses . 12-16 table 12-32. cpu to at bus and on-board i/o and rom ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 table 12-33. cpu to at-bus, on-board i/o, and rom ---- input requirements 12-17 table 12-34. 197dma to at-bus, on-board i/o, and rom ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 table 12-35. dma to at-bus, on-board i/o, and rom ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 table 12-36. dma to at-bus, on-board i/o, and rom ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 table 12-37. dma and at-bus master access to local memory ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 table 12-38. dma and at-bus master access to local memory ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 table 12-39. dma and at-bus master access to local memory ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 table 12-40. refresh ---- output responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 table 12-41. refresh ---- formula specifications . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 table 12-42. refresh ---- input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 table 12-43. miscellaneous parameters ---- output responses . . . . . . . . . . . . . . 12-21 table 12-44. miscellaneous parameters ---- formula specifications . . . . . . . . . . 12-21 table 12-45. miscellaneous parameters ---- input requirements . . . . . . . . . . . . . 12-22 table 12-46. local bus access and cache ---- output responses . . . . . . . . . . . . 12-22 table 12-47. local bus access and cache ---- formula specifications . . . . . . . . 12-22 table 12-48. local bus access and cache ---- input requirements . . . . . . . . . . . 12-23 table 12-49. output responses ---- standby refresh . . . . . . . . . . . . . . . . . . . . . . 12-23 82c836 chipset data sheet contents n chips and technologies, inc. p r e l i m i n a r y revision 3.0 xiii
section 1 82c836 chipset introduction the 82c836 (also known as scatsx) is a vlsi device incorporating the motherboard logic required to build a low-cost, highly-integrated, ibm pc/at-compatible computer. it is designed to be used in conjunction with other chips and technologies controllers such as the 82c45x vga controller and the 82c710 integrated floppy disk and multifunction controller. when used with these devices, the 82c836 acts as the heart of a highly integrated system significantly reducing motherboard size, component count, and the need for many i/o channel slots. features the 82c836 provides the following features: 80386sx control logic and clocks to support cpu speeds of up to 25mhz with zero (or one) wait states a 146818-compatible real time clock with 114 bytes of cmos ram two 8237-compatible dma controllers two 8259-compatible interrupt controllers an 8254-compatible programmable interval timer an 82284-compatible clock generation and ready interface an 82288-compatible bus controller a dram refresh controller power management features a dram controller that supports up to 16 mb of dram using 256kb, 1mb or 4mb drams a memory controller that provides shadow ram and support of either 8-bit or 16-bit bios rom support for fast local cache ram via external cache controller four ems page registers (lim ems 4.0 and 3.2 compatible) interface logic for an 80387sx numeric coprocessor interface logic for an 8042 keyboard controller fast gatea20 and fast cpu reset logic compact packaging in a single 160-pin plastic flat pack (160 pfp). chips and technologies, inc. p r e l i m i n a r y revision 3.0 1-1
the scatsx basic system architecture is shown in figure 1-1. architectural overview the major address and data buses are described in table 1-1. various memory and i/o ?? resources ?? are accessible from these buses. i/o resources contained within the 82c836 include: internal configuration registers (icrs), two dma controllers, two interrupt controllers, a real time clock (rtc) with cmos ram, timer registers and ems page registers. inbound during master cycles only. * * * at bus ua17-ua23 sa0-sa19,sbhe- cmd sd0-sd7 sd8-sd15 xd0-xd7 xd8-xd15 sdirl sdirh 8042 eprom ras,cas,ma,mwe moda0,20 command a1-a19,a21-a23,bhe- hlda ads,m/io,d/c,w/r a0-a23,bhe- d0-d7 d8-d15 par optional 80387sx npu 82c836 scatsx dram spkr 80386sx cpu sa0-sa19 figure 1-1. scatsx basic system architecture n architectural overview 82c836 chipset introduction 1-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 1-1. address and data buses pins bus name description d15-d0 cpu data a 16-bit bidirectional bus for data transfer to or from the cpu. also used during dma and master cycles for data transfer to or from dram. md15-md0 memory data a 16-bit bidirectional bus for data transfer to or from local dram. it should be connected to the d-bus though series resistors to minimize undershoot and overshoot. xd15-xd0 x-bus a 16-bit bidirectional bus for data transfer to or from on-board peripherals sd15-sd0 at bus data the main 16-bit bidirectional bus for transferring data to or from add-on cards. a23-a0 cpu addr a 24-bit bus, driven primarily by the cpu (80386sx). driven by the 82c836 during dma and refresh cycles. sa19-sa0 at bus addr the main 20-bit address bus for addressing i/o and memory resources on the at bus. ua23-ua17 unlatch addr an unlatch address bus providing the high-order address bits for memory resources on the at bus. ma10-ma0 row/col addr a multiplexed address bus driven by the 82c836 for dram row and column addressing. typical on-board i/o resources external to the 82c836 include: keyboard controller, optional numeric coprocessor, and optional real time clock (rtc). the scatsx xd-bus, subject to loading limitations, can also support an on-board video controller, floppy/hard disk controller, communications ports, parallel port, and/or game port normally residing on the at bus. on-board memory resources external to the 82c836 include the local dram and bios eprom. in general, all memory and i/o resources, whether on-board or on the at bus, are either 16-bit or 8-bit resources. 16-bit resources support 16-bit data transfer on all 16 bits of the respective data bus, as well as 8-bit data transfer to or from an odd address on data bits 8-15, or 8-bit data transfer to or from and even address on data bits 0-7. note that 16-bit resources, including the cpu itself always use data bits 0-7 for even-addressed byte transfers and data bits 8-15 for odd-addressed byte transfers. 8-bit resources, in contrast, always use data bits 0-7, regardless of even or odd addresses, and can transfer only 8 bits at a time. this disparity between 8-bit resources and 16-bit resources gives rise to two special cases in data transfer. byte swapping ---- whenever a 16-bit resource (or the cpu) transfers a data byte to or from an 8-bit resource at an odd address, the data on bits 8-15 for the 16-bit resource must be transferred to or from bits 0-7 for the 8-bit resource. the 82c836 performs this byte swapping as needed during cpu i/o or memory read/write cycles, dma cycles, and master cycles, including dma or master cycles in which both the data source and the data destination reside on the at bus. 82c836 chipset introduction architectural overview n chips and technologies, inc. p r e l i m i n a r y revision 3.0 1-3
bus conversion ---- whenever the cpu attempts to transfer a 16-bit even-address word to or from an 8-bit resource, the 82c836 converts the 16-bit cpu cycle into two consecutive 8-bit cycles. the cpu is delayed by means of wait states until both 8-bit cycles have been completed. bus conversion by the 82c836 can occur on either i/o or memory cycles, but only on cpu initiated cycles, not on dma or master cycles. the following summarizes all possible cycles types in a scatsx at-compatible architecture. cpu initiated local cycles (no command on at bus) local dram read or write interrupt acknowledge halt/shutdown cpu initiated at bus cycles (command generated on at bus) on-board rom read or write on-board i/o read or write at bus memory read or write at bus i/o read or write dma memory to i/o (simultaneous memory read and i/o write) i/o to memory (simultaneous i/o read and memory write) master memory read or write (may access on-board dram and rom) i/o read or write refresh normal (system initiated) master initiated additional variations on the above types resource: 8/16 bit, memory or i/o, on-board or at bus data transfer size: byte or word address: even or odd, first 1mb or not delay or speed-up via iochrdy or 0ws n architectural overview 82c836 chipset introduction 1-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
the major signal groups in a scatsx at-compatible architecture are as follows: at bus interface signals, 8-bit section xd7:0, sdirl (sd0-7) a19:0, moda0 (sa0-19) hlda (aen), -refresh ale -lomegcs (-smemr, -smemw) -xior, -xiow iochrdy, -0ws -iochck, irq3-7, irq9 dreq1-3, -dack[1-3], tc xrst (resetdrv), busclk, osc2 at bus interface signals, 16-bit extension xd15:8, sdirh (sd8:15) a23:17, moda20, -bhe, -memcs16, -iocs16 -master -xmemr, -xmemw irq10-12, irq14:15 dreq0, dreq5-7, -dack[0, 5-7] other 82c836 signals d0-15 -ads, -ready, m/-io, d/-c, w/-r, -na hold, intr, nmi, pwrgood, cpurst cxin, procclk, osc1 ma0-9, ras0-3, -casl, -cash, -mwe, parl, parh -romcs, 8042cs, -reset2, 32khz/irq8, ps/-rtccs, spkout -npbusy, -nperr, -busy note: signals listed above are 82c836 signals. certain closely related at bus equivalent signals are shown in parentheses in cases where the correlation between 82c836 and at bus signals may not be readily apparent. 82c836 chipset introduction architectural overview n chips and technologies, inc. p r e l i m i n a r y revision 3.0 1-5
table 1-2 lists the key signals that signify bus ownership. additional information on signal functions and timing relationships is found in section 11, system timing relationships and section 12, system characteristics , subsection titled ac characteristics . table 1-2. bus ownership hlda aen -master -refresh bus owner l l h h system cpu h h h h dma controller h l l h add-on card bus master h h h l refresh, initiated by system h l l l refresh, initiated by master while -master is inactive, aen should follow hlda. when -master is active, aen should be forced low . n architectural overview 82c836 chipset introduction 1-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 2 pin assignments pin assignments the 82c836 chipset single-chip 386sx at is packaged in a 160-pin plastic flat pack package. figure 2-1. shows the top view of the chip layout. figure 2-1. 160-pin pfp pinout (top view) chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-1
signal descriptions a signal name prefixed by a hyphen, such as -ras0, specifies an active-low signal. tables 2-1 through 2-6 describes the functions and characteristics of the signals on each pin or group of pins for the 82c836 chipset. table 2-1. clock input and output signals pin type name description 122 input osc1 14.318mhz crystal oscillator input, either from an external oscillator module or from a crystal that is also tied to osc2. the 82c836 circuit is an inverting amplifier and relies on low crystal impedance at resonance (i.e. series resonance). 121 output osc2 14.318mhz crystal oscillator output from the internal crystal oscillator. if an external oscillator module is used, leave osc2 unconnected. 3 input cxin cpu clock oscillator input from an external oscillator. serves as the source for procclk. 2 output procclk processor clock output to the 80386sx processor. the frequency of procclk is twice the processor?s internal clock frequency. 56 output busclk bus clock output to the 8042 and at bus. n signal descriptions pin assignments 2-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 2-2. local bus interface signals pin type name description 5-18 bidirectional a<0:13> ---- 20-21 bidirectional a<14:15> ---- 23-30 bidirectional a<16:23> cpu address, bits 0-23. a0 is also known as -ble. these signals are driven by the cpu during cpu generated bus cycles, by the 82c836 during refresh and dma cycles, and by the add-in card bus master (via address buffers) during master cycles. 58 bidirectional moda0 modified a0 is the internally latched state of cpu address bit a0 during cpu generated bus cycles. the 82c836 toggles this bit during conversion cycles. the 82c836 also controls moda0 during refresh and dma cycles, and the add-in card bus master controls it (via address buffers) during master cycles. 98 bidirectional moda20 modified a20 is gated a20 from the 82c836?s gate a20 logic and should be used instead of cpu a20. moda20 is an input during master cycles. 33 bidirectional -bhe byte high enable is an input from the 80386sx during cpu and master cycles, and an output during dma cycles. -bhe and a0 indicate the type of bus transfer. -bhe is pulled high internally. bhe a0 function 0 0 word transfer 0 1 odd byte transfer 1 0 even byte transfer 1 1 reserved 160 bidirectional d00 ---- 158 bidirectional d01 ---- 156 bidirectional d02 ---- 154 bidirectional d03 ---- 152 bidirectional d04 ---- 150 bidirectional d05 ---- 148 bidirectional d06 ---- 146 bidirectional d07 ---- 159 bidirectional d08 ---- 157 bidirectional d09 ---- 155 bidirectional d10 ---- 153 bidirectional d11 ---- 151 bidirectional d12 ---- 149 bidirectional d13 ---- 147 bidirectional d14 ---- 145 bidirectional d15 cpu data bus, bits 0 to 15. pin assignments signal descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-3
table 2-2. local bus interface signals (continued) pin type name description 4 input -ads processor address strobe from the 80386sx. provides timing markers for new address and start of cycle. tri-stated during a hold acknowledge state. 31 input w/-r processor write/read status. indicates whether the cpu cycle is a write or read. 32 input d/-c processor data/control status. indicates whether the cpu cycle is a data access or code/control cycle. 34 input m/-io memory or i/o select from cpu. indicates whether the cpu cycle is a memory access or an i/o. 37 bidirectional -ready active-low signal indicates the end of a cycle. -ready is normally controlled by the 82c836 and should be connected to the 80386sx -ready input. for external cache and coprocessor support, this signal can be programmed to operate as an input. 137 output -na (-stcyc) next address request to the 80386sx. requests the cpu to enter pipeline mode if possible. can be programmed to operate as a cpu cycle start indicator instead of -na if desired. usable as an address latch (-adrl) control in either case. 36 output hold hold request is an active-high output to the processor that requests bus access for refresh, dma or master cycles. hold should be connected to the processor?s hold input. 35 input hlda hold acknowledge is an active-high input from the processor indicating when the cpu local bus has been given up by the processor. hlda should be connected to the 80386sx processor?s hlda pin. 143 output nmi non-maskable interrupt is generated as a result of a parity error or an i/o channel error (-iochck). nmi should be connected to the processor?s nmi input. the 80386sx responds to a low-to-high transition on nmi. 144 output intr interrupt request is an active-high request to the cpu to suspend the current process and acknowledge the request. intr should be connected to the intr input to the cpu. n signal descriptions pin assignments 2-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 2-3. numeric coprocessor interface signals pin type name description 133 output -busy numeric coprocessor busy status output to the 80386sx. this signal normally echoes the state of -npbusy from the 80387sx. during coprocessor error conditions, it is held low. also, it is pulsed repetitively by the 82c836 when no coprocessor is present. 127 input -npbusy busy status from 80387sx. this signal indicates the 80387sx is currently executing a command. 128 input -nperr error signal from the coprocessor. table 2-4. memory interface signals pin type name description 108-117 output ma0-ma9 multiplexed dram address bits ma 0 to 9 are outputs to the drams 107-104 output -ras<0:3>, (ma10) row address strobes 0 to 3 are active-low strobes used as ras controls for the banks of dram. each bank is 18 bits wide (including 2 bits for parity). each byte is addressed with an even or odd cas signal. -ras<0:3>, perform different functions in an encoded ras mode. when using a 4mb dram configuration, -ras3 becomes ma10. for further details, refer to section 5, system interface , subsection titled dram interface . 101 output -cash column address strobe high is an active-low output to all high (odd) byte drams. 100 output -casl column address strobe low is an active-low output to all low (even) byte drams. 119 bidirectional parh parity high is the parity bit from the high-order bytes of the drams. 118 bidirectional parl parity low is the parity bit from the low-order bytes of the drams. 103 output -mwe memory write enable is an active-low output connected to all drams. -mwe is normally low, but is high for read cycle. this signal can also be used directly to control the direction of the transceivers (if present) that buffer the dram data to or from the cpu local data bus. 38 output -romcs rom chip select is an active-low output to the eprom(s). -romcs becomes active for the progammed address range. pin assignments signal descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-5
table 2-5. i/o channel interface signals pin type name description 60-61 bidirectional xd0<0:1> ---- 63-76 bidirectional xd0<2:15> 16-bit system data bus for on-board i/o, on-board rom and (via buffers) at bus data. 136 output sdirh ---- 135 output sdirl channel data bus controls are outputs that control the direction of the data buffer between the xd-bus and the sd-bus. when the signals are high (default), data flows from xd to sd; when the signals are low, data flows xd from sd. 97 input -master master is an active-low input from the i/o channel?s 16-bit extension. -master allows a microprocessor, or dma controller, residing on the i/o channel to control the system, address, data, and control lines. 124 bidirectional -refresh memory refresh control is an active-low output to the i/o channel that indicates a refresh cycle. during master cycles, -refresh is an input to the 82c836. 57 output ale address latch enable is an active-high output used to latch valid addresses on the i/o channel. ale is held continuously high during refresh, dma, and master cycles. 79 bidirectional -xior i/o read command is an active-low output used by i/o devices to put their data on the bus. this signal is used by on-board peripherals as well as the i/o channel. during master cycles, -xior is an input command to the perpherals and the 82c836. 80 bidirectional -xiow i/o write command is an active-low output used by i/o devices to capture data from the bus. this signal is used by on-board peripherals as well as the i/o channel. during master cycles, -xiow is an input command to the peripherals and the 82c836. 77 bidirectional -xmemr memory read command is an active-low output used by xd-bus, video memory, and i/o channel memory. during master cycles, -xmemr is an input command to the peripherals and the 82c836. during memory refresh and dma cycles, -xmemr is always an output. 78 bidirectional -xmemw memory write command is an active-low output used by xd-bus, video memory, and i/o channel memory. during master cycles, -xmemw is an input command to the peripherals and the 82c836. during memory refresh and dma cycles, -xmemw is always an output. 131 output -lomegcs low meg chip select is an active-low output that is a decode of memory accesses below 1mb. this output is used to gate -smemr and -smemw onto the at bus (8-bit section) from -xmemr and -xmemw, respectively. -lomegcs operates in this manner for dma and master cycles as well as cpu cycles. n signal descriptions pin assignments 2-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 2-5. i/o channel interface signals (continued) pin type name description 41 input iochrdy i/o channel ready is used by i/o channel or xd-bus devices to lengthen their r/w cycles. normally, iochrdy is high; it is pulled low to extend the cycle time. this input should be driven by an open collector driver. 40 input -0ws (-lba) zero wait-state is an active-low input from the i/o channel. this signal allows the present bus cycle to terminate without inserting any additional wait-states -0ws should be driven with an open collector or a tri-state driver. for external cache support, this signal can also be programmed to act as a local bus access (-lba) input as well as the at bus -0ws input. 83 bidirectional -iocs16 i/o 16-bit chip select is an active-low signal. -iocs16 is an input from the i/o channel and xd-bus peripherals, indicating that the accessed resource can support 16-bit data transfers. -iocs16 is an output for i/o accesses to the ems i/o ports. -iocs16 should be driven with an open collector or tri-state driver. 82 bidirectional -memcs16 memory 16-bit chip select is an active-low signal. -memcs16 is an input from the i/o channel and xd-bus peripherals, indicating that the accessed resource can support 16-bit data transfers. -memcs16 is an output for cpu or master accesses to on-board dram or to 16-bit on-board rom. 42 input -iochck i/o channel check is an active-low signal from the i/o channel used to trigger an nmi in the processor in the event of an unrecoverable i/o channel error. 54-50 input irq0<3:7> ---- 49 input irq09 ---- 84-86 input irq<10:12> ---- 88-87 input irq<14:15> interrupt requests 3-7, 9, 10-12, 14-15 are asynchronous inputs to the 82c836 interrupt controllers. these requests are prioritized with irq03 having the highest priority and irq15 the lowest. the request line is held active until acknowledged by the processor with an interrupt acknowledge cycle. 90 input drq0/dselb ---- 48 input drq1/dsela ---- 46 input drq2/drqa ---- 44 input drq3/drqb ---- 92 input drq5/-cas3h ---- 94 input drq6/-cas2h ---- pin assignments signal descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-7
table 2-5. i/o channel interface signals (continued) pin type name description 96 input drq7/-cas1h dma request 0-3, 5-7 are asynchronous requests used by peripherals to request dma services. these requests are prioritized with drq0 having the highest priority and drq7 the lowest. drq must be held active until the corresponding dma acknowledge (dack) line goes active. in mra mode, the functions of these pins change as indicated. 89 output -dack0/-dacken ---- 47 output -dack1/dacka ---- 45 output -dack2/dackb ---- 43 output -dack3/dackc ---- 91 output -dack5/-cas3l ---- 93 output -dack6/-cas2l ---- 95 output -dack7/-cas1l dma acknowledge 0-3, 5-7 are active-low acknowledge signals issued by the 82c836 after a dma service request (via a drq line) and successful arbitration. during power-on reset, these signals are used for reset strap options. in mra mode, the functions of these pins change as indicated. 55 output tc terminal count is an active-high output pulse to the i/o channel that indicates the end of a dma transfer. table 2-6. miscellaneous signals pin type name description 39 input pwrgood power good is an active-high input from the power supply. when this signal is high, it indicates all power supply voltages have reached their working levels. cpurst (pin 138) and xrst (pin 134) remain high for at least 200 m s after pwrgood goes high. 138 output cpurst cpu reset is an active-high output that resets the 80386sx processor. cpurst goes active at power-up or during a software-initiated cpu reset. cpurst without xrst is often used to return the cpu to real mode from protected mode. 134 output xrst peripheral reset is an active-high output that resets external peripherals and the coprocessor (if present) during power-up. 132 output spkout speaker data is a waveform (the output of channel 2 of the timer/counter gated by bit 1 of port 61h) that is routed to an external driver circuit, a low pass filter, and then to the speaker. n signal descriptions pin assignments 2-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 2-6. miscellaneous signals (continued) pin type name description 141 bidirectional mfp5 multi function pin 5 is a bidirectional pin that has two functions (see -dack5 in ?? reset strap options ?? ): in internal rtc mode, mfp5 is the power sense (ps) input, active high, indicating the state of the battery. the ps signal should be powered from the battery back-up circuit. in external rtc mode, mfp5 is the real time clock chip select (-rtccs) active low. it is a decode of the i/o address range 070h-071h. 140 input mfp4 multi function pin 4 is an input that has two functions (see -dack5 in ?? reset strap options ?? ). in internal rtc mode, mfp4 is the 32khz oscillator input, which should be connected to a square wave source with a frequency of 32.768khz. this input signal is the timing reference for the internal rtc of the 82c836. in external rtc mode, mfp4 is interrupt request 8 (irq08) from the external rtc. 126 input mfp3 multi function pin 3 is an input pin driven by the -reset2 signal from the 8042 keyboard controller. in response to this input (active low), the 82c836 generates cpurst to reset the cpu. the signal is under software control via the 8042. this pin may have an alternate function in a future version of the 82c836, but only the -reset2 function is available at present. 130 output mfp2 multi function pin 2 is an output pin used for 8042 chip select (-8042cs). this signal, an active-low output to the 8042 keyboard controller, is a decode of the i/o address range 060h-06fh. this pin may have an alternate function in a future verison of the 82c836, but only the -8042cs function is available at present. 129 input mfp1 multi function pin 1 is an input pin driven by the gatea20 signal from the 8042 keyboard controller. in response to a low level on this pin, the 82c836 keeps moda20 low during cpu cycles (depending on fast gatea20, port 92h). a high level on gatea20 allows moda20 to follow a20. this pin may have an alternate function in a future version of the 82c836, but only the gatea20 function is available at present. 125 input mfp0 mutli function pin 0 is an input pin acting as interrupt request 1 (irq1). this signal, an active-high input from the 8042 keyboard controller, is used by the 82c836?s internal interrupt controller. this pin may have an alternate function in a future version of the 82c836, but only the irq1 function is available at present. signal pinouts the signal pinouts for the 82c836 chipset are summarized in tables 2-7 and 2-8. pin assignments signal pinouts n chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-9
table 2-7. alphabetical pin definitions signal name pin signal name pin signal name pin signal name pin -0ws/-lba 40 d06 148 irq12 86 -refresh 124 a00 5 d07 146 irq14 88 -romcs 38 a01 6 d08 159 irq15 87 sdirh 136 a02 7 d09 157 -lomegcs 131 sdirl 135 a03 8 d10 155 ma0 108 spkout 132 a04 9 d11 153 ma1 ma1 109 tc a05 10 d12 151 ma2 110 vcc 19 a06 11 d13 149 ma3 111 vcc 62 a07 12 d14 147 ma4 112 vcc 102 a08 13 d15 145 ma5 113 vcc 139 a09 14 -dack0 89 ma6 114 vss 1 a10 15 -dack1 47 ma7 115 vss 22 a11 16 -dack2 45 ma8 116 vss 59 a12 17 -dack3 43 ma9 117 vss 81 a13 18 -dack5 91 -master 97 vss 99 a14 20 -dack6 93 -memcs16 82 vss 120 a15 21 -dack7 95 mfp0 125 vss 123 a16 23 d/-c 32 mfp1 129 vss 142 a17 24 drq0 90 mfp2 130 w/-r 31 a18 25 drq1 48 mfp3 126 xd00 60 a19 26 drq2 46 mfp4 140 xd01 61 a20 27 drq3 44 mfp5 141 xd02 63 a21 28 drq5 92 m/io 34 xd03 64 a22 29 drq6 94 moda0 58 xd04 65 a23 30 drq7 96 moda20 98 xd05 66 -ads 4 -error 128 -mwe 103 xd06 67 ale 57 hlda 35 -na/-stcyc 137 xd07 68 -bhe 33 hold 36 nmi 143 xd08 69 busclk 56 intr 144 -npbz 127 xd09 70 -busy 133 -iochck 42 osc1 122 xd10 71 -cash 101 iochrdy 41 osc2 121 xd11 72 -casl 100 -iocs16 83 parh 119 xd12 73 cpurst 138 irq03 54 parl 118 xd13 74 cxin 3 irq04 53 procclk 2 xd14 75 d00 160 irq05 52 pwrgood 39 xd15 76 d01 158 irq06 51 -ras0 107 -xior 79 d02 156 irq07 50 -ras1 106 -xiow 80 d03 154 irq09 49 -ras2 105 -xmemr 77 d04 152 irq10 84 -ras3/ma10 104 -xmemw 78 d05 150 irq11 85 -ready 37 xrst 134 n signal pinouts pin assignments 2-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 2-8. numerical pin definitions pin signal name pin signal name pin signal name pin signal name 1 vss 41 iochrdy 81 vss 121 osc2 2 procclk 42 -iochck 82 -memcs16 122 osc1 3 cxin 43 -dack3 83 -iocs16 123 vss 4 -ads 44 drq3 84 irq10 124 -refresh 5 a00 45 -dack2 85 irq11 125 mfp0 6 a01 46 drq2 86 irq12 126 mfp3 7 a02 47 -dack1 87 irq15 127 -npbz 8 a03 48 drq1 88 irq14 128 -error 9 a04 49 irq09 89 -dack0 129 mfp1 10 a05 50 irq07 90 drq0 130 mfp2 11 a06 51 irq06 91 -dack5 131 -lomegcs 12 a07 52 irq05 92 drq5 132 spkout 13 a08 53 irq04 93 -dack6 133 -busy 14 a09 54 irq03 94 drq6 134 xrst 15 a10 55 tc 95 -dack7 135 sdirl 16 a11 56 busclk 96 drq7 136 sdirh 17 a12 57 ale 97 -master 137 -na 18 a13 58 moda0 98 moda20 138 cpurst 19 vcc 59 vss 99 vss 139 vcc 20 a14 60 xd00 100 -casl 140 mfp4 21 a15 61 xd01 101 -cash 141 mfp5 22 vss 62 vcc 102 vcc 142 vss 23 a16 63 xd02 103 -mwe 143 nmi 24 a17 64 xd02 104 -ras3 144 intr 25 a18 65 xd04 105 -ras2 145 d15 26 a19 66 xd05 106 -ras1 146 d07 27 a20 67 xd06 107 -ras0 147 d14 28 a21 68 xd07 108 ma0 148 d06 29 a22 69 xd08 109 ma1 149 d13 30 a23 70 xd09 90 drq0 150 d05 31 w/-r 71 xd10 91 -dack5 151 d12 32 d/-c 72 xd11 92 drq5 152 d04 33 -bhe 73 xd12 93 -dack6 153 d11 34 m/-io 74 xd13 94 drq6 154 d03 35 hlda 75 xd14 95 -dack7 155 d10 36 hold 76 xd15 96 drq7 156 d02 37 -ready 77 -xmemr 97 -master 157 d09 38 -romcs 78 -xmemw 98 moda20 158 d01 39 pwrgood 79 -xior 99 vss 159 d08 40 -0ws 80 -xiow 100 -casl 160 d00 pin assignments signal pinouts n chips and technologies, inc. p r e l i m i n a r y revision 3.0 2-11
section 3 functional description configuration registers the 82c836 contains an extensive and versatile set of internal configuration registers (icrs) for enabling or disabling various optional modes and features. the internal configuration registers are accessed using i/o ports 22h and 23h. to read or write an internal configuration register, the register number (index) should be output to port 22h, and the contents of the register then read or written at port 23h. each read or write to port 23h must be preceded by an output to port 22h, even if the index value written to port 22h is unchanged from the last access. reset strap options the 82c836 features reset strap options without having to use extra pins. the 82c836 uses -dack lines to implement the strap options. the -dack lines are normally outputs, but during power-up they are used as input signals. these lines are sampled during the high state of xrst after pwrgood goes high. later, they convert to outputs for normal functions. a 4.7k ohm pull-down or pull-up resistor pulls the signals low or high for strap option sampling. table 3-1 describes the pins used for strap options. figure 3-1 shows an alternate way to implement a pull-low function in cases where a simple pull-down resistor is not suitable because of signal loading. note: the circuit shown in figure 3-1 should not be used in systems using standby refresh in mra mode. chips and technologies, inc. p r e l i m i n a r y revision 3.0 3-1
table 3-1. pins for strap options signal strap function description -dack0 sense0 determines icr 45h bit 0 -dack1 sense1 determines icr 45 bit 1 -dack2 video video on sd - or xd bus ; also determines icr 45h bit 2 -dack3 na/stcyc -na - or -stcyc function -dack5 -exrtc internal rtc - or external -dack6 reserved (should be pulled up) -dack7 -rom16 8-bit rom - or 16-bit rom - = pull-up = pull-down sense0 and sense1 are general purpose and can be used according to specific system requirements. -dack2 can also be used as a general purpose sense2 if icr44h is appropriately programmed to specify where the video controller resides. if external real time clock is used (-dack5 pulled low), the -rtccs pin (mfp5) should be connected to pwrgood through a diode as shown in figure 3-2. this insures that the standby enable bit (icr 60h) will always be cleared on power-up. otherwise, the 82c836 could power-up with standby mode enabled, which would prevent -dack5 from being sampled properly. see the icr 60h description in section 4, configuration registers for further explanation of standby initialization. -xrst 7407 +5v -dackn 10k figure 3-1. pull-low function ---- alternate implementation n reset strap options functional description 3-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
battery backup and power-up/down most applications require the real time clock to remain active whenever the system power is turned off. to accomplish this, the user must provide an alternate source of power to the 82c836. this alternate source of power is normally provided by connecting a battery to the v cc supply pin of the device. a means should be provided for switching between the system power supply and the battery. a circuit such as the one shown in figure 3-3 may be used to eliminate power drain on the battery when system power is available. the circuit allows reliable transitions between system and battery power without undue battery power drain. the battery voltage should not be high enough to cause a net increase in back-up voltage when normal power is turned off. otherwise, the 82c836 and 32khz oscillator will continue to be powered by the battery even when the power supply is turned on, and battery drain will actually increase when power is on due to reverse conduction through the pnp transistor (2n3906). 1n4148 pwrgood 39 82c836b 141 (mfp5) -rtccs figure 3-2. ps diode for external real time clock systems functional description battery backup and power-up/down n chips and technologies, inc. p r e l i m i n a r y revision 3.0 3-3
a similar precaution is needed during vcc ramp up or ramp down. the vcc ?? changeover ?? threshold, determined by r1 and r2 should be high enough so that the 2n3906 cannot remain on when vcc is less than 4vdc. otherwise, depending on battery voltage, the 2n3906 may again reverse conduct and load down the battery momentarily as vcc is ramping up or down. the user should also ensure that the vin maximum specification for the 82c836 is never exceeded when powering the system up or down. failure to observe this specification may result in damage to the device. the three diodes in series with the battery provide roughly 1.8vdc voltage drop between the battery and the 82c836, as well as protecting the battery from possible explosion in the event of accidental polarity reversal. (safety agencies generally require a minimum of two series diodes or one diode and a series resistor.) a pin is provided in the 82c836 to protect the contents of the real time clock and reduce power consumption whenever the system is powered down. the pwrgood pin should be low whenever the system power supply is not within specifications for proper operation of the system. this signal may be generated by circuitry either in the power supply or on the system board. the pwrgood input disables all unnecessary figure 3-3. battery backup circuit n battery backup and power-up/down functional description 3-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
inputs during the time the system is powered down to prevent noise on the inactive pins from causing increased icc. this pin must therefore be active (high) for the remainder of the device to operate properly when system power is applied. as most at-compatible architectures, the reset and power good functions normally available separately on an mc146818 are combined in the 82c836. the pwrgood input serves not only as a power down control pin, but also as a general hardware reset input. it does not reset the real time clock. another pin is provided to initialize the real time clock (rtc) whenever system or battery power is first applied to the 82c836. the ps/mfp5 pin does not alter the cmos ram or clock/calendar contents, but it does initialize the necessary rtc control register bits. deassertion of power sense (ps) disables the generation of rtc interrupts and sets a flag indicating that the contents of the real time clock may not be valid. a recommended circuit for controlling the ps input is also shown in figure 3-3 above (refer to applicable product alerts for the 82c836a circuit). testability all unnecessary inputs are disabled while pwrgood is low. in addition, all outputs except osc2 are held in a high-impedance state. osc2, the 14.3mhz output driver, is driven to a continuously low logic level. for in-circuit manufacturing test, the ps input should also be pulsed low momentarily while pwrgood is low to insure that the 82c836 is fully reset. standby power management and laptop support the 82c836b includes the following features for stand-by power management in laptop applications: when the system has been powered down except for scatsx and dram, scatsx can automatically switch from normal 14.318mhz based dram refresh to 32khz based dram refresh. this allows the contents of dram to be preserved during power-down. icr 60h is used to enable or disable the stand-by refresh capability. if the stand-by refresh capability is enabled, scatsx automatically switches to stand-by refresh in response to a logic low level on the pwrgood input. stand-by refresh is designed to utilize the cas-before-ras mode. in this mode of refresh, the refresh address is generated internally by the dram and is not provided by the 82c836b. icr 60h is used to enable or disable cas-before-ras refresh. if the cas-before-ras refresh mode is enabled, it applies during normal powered-on operation as well as during power down intervals. functional description standby power management and laptop support n chips and technologies, inc. p r e l i m i n a r y revision 3.0 3-5
the refresh interval during stand-by refresh is programmable: 15 m s, 122 m s, 244 m s, or 488 m s between refreshes (.5, 2, 4, or 8 cycles of the 32.768khz input frequency). the power sense input (ps/mfp5) must remain high during power down in order for stand-by refresh to work. a logic low level on ps while pwrgood is low will clear the stand-by enable bit in icr 60h. since pwrgood is low, scatsx will then become fully reset. during power-down stand-by refresh, the following output signals remain active instead of becoming high impedance: -cas3, -cas2, -cas1 (if multiple ras active mode is enabled). refer to section 5, system interface , subsection titled memory interface for a detailed discussion of the multiple ras active mode and 4mb dram configurations. -cas0, -mwe, -ras0, -ras1, -ras2. -ras3 (if not using a 4mb dram configuration). refer to section 5, system interface , subsection titled memory interface for a detailed discussion of the multiple ras active mode and 4mb dram configurations. if a 4mb dram configuration is used, ma10 is actively driven to a continuous logic high level. ma0-9 are actively driven to a continuous logic high level. osc2 remains actively driven to a continuous logic low level; this is always the case during power-down even if the standby refresh is disabled. during normal powered-on operation, the 82c836b can optionally generate fast 8-bit timing or true 16-bit cycles for video i/o and/or video memory accesses in selected programmable address ranges (see icr 61h and 62h). this capability is designed to improve video performance in products that use on-board video subsystems, including very compact laptop and notebook pc?s with 8-bit video interfaces. operational power management average system power consumption can be reduced by slowing or stopping the processor clock during idle periods. if a nonstatic cpu is used, the processor clock can be slowed down. if a static cpu is used, the processor clock can be stopped completely. in the 82c836, ?? sleep ?? mode is provided in which a halt instruction, executed by the cpu, triggers the slowing or stopping of procclk. the sleep mode is enabled by bit 7 in internal configuration register 46h, and bits 1 and 0 determine the frequency of procclk during sleep mode. the sleep frequency is selectable between 0 (procclk stopped), cxin/2, cxin/4 or cxin/8. n operational power management functional description 3-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
bits 3 and 2 in icr 46h determine the normal or ?? run ?? mode frequency of procclk, selectable between cxin, cxin/2, cxin/4 or cxin8. the run mode is applicable whenever: the sleep mode is disabled; or an interrupt (or nmi) has occurred in the case of an interrupt, run mode continues until a subsequent halt cycle. in the case of a dma, refresh or master operation, sleep mode resumes upon completion of the operation. reset also returns the system to run mode. dma, refresh, and master operations always occur with procclk = cxin, regardless of run and sleep frequency settings. functional description operational power management n chips and technologies, inc. p r e l i m i n a r y revision 3.0 3-7
section 4 clock/bus control clock generation the 82c836 clock generator produces the signals shown in figure 4-1. 1/6 dmaclk internal 1,1/2 busclk procclk 1/4,1/5 8mhz typical sysclk internal 1/2 1/8 0,1/2,1/4, sleep 1/8 1,1/2,1/4, run cxin 32mhz,40mhz,50mhz figure 4-1. clock generation chips and technologies, inc. p r e l i m i n a r y revision 3.0 4-1
procclk (processor clock) is an output clock for the 80386sx processor. procclk can be set (with internal configuration register 46h, bits 3-2) for the following values: procclk = cxin procclk = cxin/2 procclk = cxin/4 procclk = cxin/8 procclk can also be halted in order to implement power management techniques. the effective speed of the 80386sx is always half the procclk frequency; e.g. for an 80386sx speed of 20mhz, procclk must be 40mhz. procclk is derived from an external crystal oscillator connected to cxin. busclk (bus clock) is an output clock for the i/o channel. busclk can be set (with internal configuration register 41h, bits 3-2) for the following values: busclk = cxin/4 busclk = cxin/5 busclk = cxin/6 the procclk selection does not affect busclk in either run or sleep modes. osc2 (oscillator) is a 14.31818mhz output signal used by the i/o channel. the oscillator can be derived from an external crystal connected to pins osc1 and osc2, or from an external oscillator connected to osc1 (leaving osc2 unconnected). dmaclk (dma clock) is an internal clock used by dma controllers to time dma operations. dmaclk can be set (with internal configuration register 01h, bit 0) to the following values: dmaclk = busclk dmaclk = busclk/2 (at-compatible) sysclk (system clock) is an internal t-state clock used by 82c836 logic. the frequency of sysclk is always procclk/2. system reset and clock synchronization scatsx supports several different reset signals: pwrgood is the main hardware reset input to the 82c836. xrst is the main hardware reset output from the 82c836. it resets everything except the cpu. cpurst is the cpu reset signal generated by the 82c836. it resets only the cpu. -reset2 (mfp3) comes from the 8042 keyboard controller and triggers resetting of the cpu only (cpurst). n system reset and clock synchronization clock/bus control 4-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
after pwrgood goes high, indicating that all voltages are within specification, the 82c836 generates reset pulses on xrst and cpurst to reset the system and cpu. while xrst is active, the dack lines are sampled and latched for the strap options. the 82c836 also samples and latches -nperr from the coprocessor to determine whether or not a coprocessor is present. the timing of the falling edges of xrst and cpurst is critical for proper clock synchronization. system timing generated by the cpu consists of t-states, each of which consists of two cycles of procclk. the 80386sx and 80387sx contain internal ?? phase ?? clocks that track the first and second procclk cycle of each t-state. for proper system operation, it is essential to synchronize both of these phase clocks and a similar phase clock inside the 82c836. an external cache controller, if implemented, also needs a phase clock if it relies on -ads and -ready for cycle tracking. the master phase clock for the entire system is the 82c836 phase clock, which is a free running divide-by-two from procclk. the 82c836, in turn, precisely controls the timing of xrst and cpurst to synchronize all other phase clocks throughout the system. there is no provision for synchronizing the 82c836 master phase clock to an external source; rather, all external phase clocks must be synchronized to the 82c836 by means of xrst or cpurst. see section 11, system timing relationships for additional timing information. bus control arbitration and basic timing the 82c836 supports an ibm pc at-compatible i/o channel, also known as the at bus. an internal bus controller, which is functionally similar to an 82288 bus controller, provides command generation and timing control for the at-compatible i/o channel. this allows the processor to run faster than the i/o channel, dma commands, and timing. accesses to the i/o channel can be programmed to run slower than the local bus cycles. although the local bus is normally controlled by the cpu, the 82c836?s internal dma controller or refresh controller can request control by issuing a hold request to the cpu. when this occurs, the 80386sx relinquishes control and issues hlda (hold acknowledge) to the 82c836. the conditions capable of triggering hold are as follows: system initiated refresh ---- 82c836 issues hold without any external prompting, based on the at-compatible refresh timer. dma request ---- 82c836 issues hold in response to a dreq input. upon receiving hlda, the 82c836 asserts the appropriate dack signal. next, depending on whether or not the dma channel has been programmed for ?? cascade ?? mode, the 82c836 generates one or more dma cycles or waits for -master to be asserted by an add-in card bus master. (see section 8, dma controller , subsection titled dma controller ---- 8237 compatible ), master request ---- 82c836 follows the same dreq/dack protocol as for dma, then waits for the add-on master to perform master cycles as needed and eventually release dreq. if the master initiates a refresh (by driving -refresh low), the 82c836 clock/bus control bus control arbitration and basic timing n chips and technologies, inc. p r e l i m i n a r y revision 3.0 4-3
performs the refresh then returns control to the master following deassertion of -xmemr. hold and hlda remain asserted continuously throughout all master cycles, including master initiated refresh. the 82c836 incorporates a state machine that generates i/o channel bus cycles for all cpu cycles not claimed by the internal memory address decode logic. the state machine synthesizes the address strobe signal (ale), the bus command signals (-xior, -xiow, -xmemr, and -xmemw), and moda0 and moda20. it monitors the state of the -iocs16 and -memcs16 signals to determine if the device on the bus is capable of 16-bit operations for i/o and memory, respectively. if a 16-bit operation is attempted with an 8-bit device, the 82c836 performs conversions of 16-bit cpu operations to paired 8-bit at bus cycles. the 82c836 supports xd-bus peripherals. internal configuration register 44h controls the sdirh and sdirl signals for different peripherals. 16-bit x-bus resources (other than rom) must generate -memcs16 and/or -iocs16 just as any 16-bit add-on card would. the 82c836 itself asserts -memcs16 and/or -iocs16 as follows: the 82c836 asserts -memcs16 during cpu, dma or master accesses to rom if it is 16-bits wide, and during cpu, dma or master accesses to local dram. the 82c836 asserts -iocs16 during accesses to ems i/o ports 2x8h and 2x9h (x = 0 or 1, programmable), which operate as a 16-bit i/o resource. although the coprocessor operates as a 16-bit i/o resource in most respects, the 82c836 does not assert -iocs16 during coprocessor accesses. the cpu local bus and the at bus are tightly coupled. activity on either bus directly corresponds to similar activity on the other bus (the at bus, however, remains idle during certain cpu local bus operations). the general start/end protocol for each bus cycle is as follows: on the cpu local bus, the start of a cpu controlled bus cycle is indicated by the low-to-high transition of -ads, and the end of the cycle is indicated by -ready being active at the end of a subsequent t-state. the t-state, in which -ads goes high, is equivalent to an 80286 ts state. this is true for either pipelined or nonpipelined 80386sx cycles. an 80386sx t1-t2-t2 sequence is equivalent to an 80286 ti-ts-tc sequence (ti = idle state). virtually no useful work can be performed by the 82c836 during a t1 state because the cpu address and status signals are not guaranteed to be valid until after the middle of t1. an 80386sx t1p-t2p sequence is equivalent to an 80286 ts-tc sequence, and useful work can be started during t1p. on the at bus, the start of a cpu generated bus cycle is indicated by an ale pulse, followed by an i/o or memory command signal going active (low). the end of the cycle is indicated by the command signal going inactive. the unlatched address (ua17-23) must be valid before the end of the ale pulse; and remains valid for a short hold time after the start of command. the latched address (sa0-19) must be valid before the start of command; and must remain valid for a short hold time after the end of command. read data must be valid before the end of the command pulse; and must remain valid for a short hold time after the end of command. write data n bus control arbitration and basic timing clock/bus control 4-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
must be valid near the beginning of command; and must remain valid for a short hold time after the end of command. the command active time can be lengthened by deasserting iochrdy, or (in most cases) shortened by asserting 0ws. master cycles on the at bus follow the same protocol as cpu controlled cycles, except ale remains continuously active (high), and unlatched address timing follows latched address timing. address and command signals are controlled by the add-on card bus master during master cycles. dma cycles on the at bus follow the same basic protocol as master cycles except the 82c836 controls the address and command signals, and commands always occur in pairs (i/o read and memory write, or memory read and i/o write). the minimum cpu local bus cycle in pipelined mode is two t-states, which occurs most often on cas-only accesses to local memory (see section 5, system interface , subsection titled rom/shadow ram interface ). in nonpipelined mode, the corresponding minimum is three t-states, which the 82c836 assures by appropriately controlling the timing of ready. if ready is controlled externally, two t-state cycles in nonpipelined mode are possible as follows: during coprocessor accesses in which the coprocessor generates -readyo soon enough to end the cycle after only two t-states. this can occur only if the 82c836 has been programmed to let the coprocessor control ready during coprocessor accesses, and if the coprocessor -readyo output has been properly interfaced to cpu -ready as described in section 5, system interface , subsection titled numeric coprocessor interface . during external cache ?? hit ?? memory reads, as discussed in section 5, system interface , subsection titled dram interface, support for external cache . detailed timing diagrams are included in system timing relationships . the 80386sx, unlike the 80286, has the ability to keep the address valid until the next address signal(na-) is asserted. during at bus accesses, the 82c836 takes advantage of this feature to eliminate the need for external address latches between cpu address and at bus address. less expensive transparent buffers (74f245 or equivalent) may be used instead of latching buffers. address bits a20 and a0 receive special treatment in at-compatible architectures such as scatsx, for the following reasons: for compatibility with the 8088 and 8086 at address ffff:10h and above; it is necessary to force a20 low during cpu accesses to memory in an 80386sx or 80286 based system. the original at-compatible approach used the gate a20 signal from the keyboard controller to accomplish this, but there is considerable time delay in this approach. with the advent of the ps/2 architectures, a ?? fast gate a20 ?? function was implemented in port92h. scatsx supports both approaches. setting 8042 gate a20 high or fast gate a20 to one allows the modified a20 to track cpu a20 during cpu accesses. during dma and master cycles, the modified a20 always tracks cpu a20, even if modified a20 is being forced low during cpu accesses. during conversion of 16-bit cpu accesses to paired 8-bit at bus cycles, a0 must be forced high during the second 8-bit cycle even though cpu a0 is still low. clock/bus control bus control arbitration and basic timing n chips and technologies, inc. p r e l i m i n a r y revision 3.0 4-5
table 4-1 summarizes the possible types of bus cycles based on bus owner, target resource type and bus, and operand type. for cpu cycles alone, there are 78 different cases; dma and master cycles account for an additional 46 and 56 cases, respectively. scatsx is designed to handle all these possible cases properly (at-compatible). table 4-1. scatsx cycle types cpu accesses target resource operand size type possible buses size direction address total cases 16-bit memory ld, xd, sd 8, 16 read/write even, odd 18 ? 16-bit input/output stx?, ld?, xd, sd 8, 16 read/write even, odd 24 ? 8-bit memory xd, sd 8, 16 read/write even, odd 12 ? 8-bit input/output stx, ld?, xd, sd 8, 16 read/write even, odd 24 ? total cases 78 ? coprocessor accesses are 16-bit if coprocessor is present, 8-bit if absent. for 16-bit operand at o dd address, cpu itself performs two 8-bit transfers; so 16-bit operand at odd address is not counted in the total cases column. cpu can also perform inta, halt, and shutdown cycles not listed. ? stx denotes a scatsx internal resource. dma transfer memory resources dma channel and i/o size i/o bus size bus direction address total cases 16-bit sd 16 ld, xd, sd read/write even 6 8-bit xd ? , sd 16 ld, xd, sd read/write even, odd 24 8-bit xd ? , sd 8 xd, sd read/write even, odd 16 total cases 46 ? dma i/o resource on xd can be fdd only (channel 2). memory resource on xd can be eprom or video ram only. scatsx can also perform refresh, not listed above. master cycles target resource operand ? size type bus size direction address total cases 16-bit memory ld, xd, sd 16 read/write even 6 16-bit memory ld, xd, sd 8 read/write even, odd 12 16-bit input/output stx, xd, sd 16 read/write even 6 16-bit input/output stx, xd, sd 8 read/write even, odd 12 8-bit memory xd, sd 8 read/write even, odd 8 8-bit input/output stx, xd, sd 8 read/write even, odd 12 total cases 56 ? master can reside on sd bus only. local bus masters are also possible using hold/hlda to get contro l, then generating cpu equivalent protocol. these cases are included in the cpu accesses section. n bus control arbitration and basic timing clock/bus control 4-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 5 system interface rom/shadow ram interface memory accesses in the range 0c0000h-0fffffh can be programmed via internal configuration registers 48h through 4ch to map to rom, local ram, or external ram, as follows: rom can be enabled or disabled in eight independent blocks of 32kb in the range 0c0000h-0fffffh. local ram can be enabled or disabled in 24 independent blocks of 16kb throughout the range 0a0000h-0fffffh. local ram the range 0c0000h-0fffffh can be write protected in eight independent blocks of 32 kb. if neither rom nor ram is enabled in a particular address block, memory accesses to that block go to the at bus. memory accesses in the range fc0000h-ffffffh are treated as follows: the default is for all memory accesses in this range go to rom in the range of 0c0000h-0fffffh, regardless of whether or not shadow ram has been enabled in the target area. there is a programmable option to reduce the size of this special area to the top 128kb (fe0000h-ffffffh) instead of the top 256kb (see icr 4e bit 4). there is another programmable option to map the affected high memory area (starting at fc0000h or fe0000h) to shadow ram instead of rom (see icr 46h bit 5). this option is intended for laptop architectures in which the initial cpu code fetches following cpu reset need to map into shadow ram instead of rom. the 82c836 provides one rom chip select (-romcs), which is active for all rom accesses. on-board rom can be either 8-bit wide or 16-bit wide and must be connected to the xd-bus. to select 16-wide width, the dack7 line must be pulled low with a 4.7k ohm resistor; to select 8-bit mode, the line must be pulled high with a 4.7k ohm resistor. the 82c836 asserts -memcs16 during all rom cycles if 16-bit mode is selected. chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-1
ram that can be accessed instead of rom in the 0c0000h-0fffffh range is called shadow ram. (ram in the 0a0000h-0bffffh range is also referred to as shadow ram.) this feature is invoked by copying an image of the bios (which is in rom) into an area of ram, thus allowing operating systems and software applications to make faster accesses to the shadowed bios (rather than rom which is much slower). the degree of performance improvement derived from the use of shadow ram depends primarily on the difference in access times between rom and dram cycles. at higher system speeds, the difference can be significant. additionally, shadow ram maintains maximum bios performance when using either a single 8-bit rom (such as a 27512) or two smaller 8-bit roms (for the same total rom capacity). using only one rom reduces component count and circuit board size. the following procedure enables shadow ram. the program that performs this procedure must reside in ram while it is executing, because rom must be disabled while writing to the shadow ram area: 1. disable interrupts. 2. copy the rom bios into ram, below the start of rom. 3. disable -romcs using internal configuration register 48h. 4. enable the shadow ram using internal configuration registers 4ah-4ch. 5. copy the bios from low dram into the area of memory allocated for shadow ram. 6. if desired, the bios can be copied in several blocks by enabling -romcs or shadow ram as needed and repeating steps 2 through 5 for each block. 7. make the shadow ram read-only, using internal configuration register 49h. 8. re-enable interrupts. dram interface the 82c836b includes a dram controller that directly supports up to 16mb of memory in four banks. the dram controller in the 82c836b is capable of operating in three possible modes: multiple ras active (mra), also known as dedicated cas in this mode, scatsx provides four ras signals and eight cas signals for controlling up to four dram banks, each bank 16-bits wide (plus two parity bits, if desired). each cas signal is dedicated to controlling one eight-bit half of one bank. page interleaved access is used whenever possible, with up to four ras signals allowed to be active at the same time. the result is very high performance in four-bank systems, since a high percentage of dram accesses can be cas-only zero wait-state accesses. mra mode is recommended for all new designs, both for performance reasons and to improve worst-case timing margins, particularly at 25mhz. the only disadvantage is that an external 74f153 and 74als138 are needed to provide seven dreq and dack signals, see figure 5-1. n dram interface system interface 5-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
single ras active (sra), also known as shared cas in this mode, scatsx provides four ras signals and only two cas signals for controlling up to four dram banks. each cas drives four half-banks, so the cas signals should be buffered in systems having more than two banks. the buffering adds delay which diminishes worst-case timing margins, particularly in 25mhz systems. in addition, the sharing of cas signals between banks means that only one ras signal can be allowed to remain active at one time. this adds an extra t-state when switching between banks (as compared to mra mode, which can switch banks in zero wait states if the new bank already has its ras signal active). the added t-state represents a significant performance penalty. the only advantage of sra mode is that the external 74f153 and 74als138 aren?t needed, since the six cas signals become dreqs and dacks, see figure 5-1. note: signal names in parentheses ( ) refer to sra mode. signal names without parentheses refer to mra mode. 74f244 -ras3/ma10 ma10 -ras3 74f153 74f153 +5v or grnd 91 92 93 94 95 96 100 101 104 134 89 43 45 47 48 90 46 44 xrst (-dack5) (drq5) (-dack6) (drq6) (-dack7) (drq7) (-casl) (-cash) (-ras3) (xrst) -dacken (-dack0) * 20k 20k 20k +5v +5v +5v +5v * * 4.7k dackc (-dack3) dackb (-dack2) dacka (-dack1) drqa drqb drq3 drq2 drq1 drq0 drq7 drq6 drq5 yb ya eb i3b ea i0b i1b i2b i0a i1a i2a i3a s0 s1 dack c b dacka : l h l l l h h l h h -dack0 -dack1 -dack2 -dack3 -dack5 -dack6 -dack7 ( none ) dsel b a l l l h h l h h drqa drqb drq0 drq5 drq1 drq6 drq2 drq7 drq3 grnd 74als138 74als138 82c836b scatsx -cas3l -cas3h -cas2l -cas2h -cas1l -cas1h -cas0l -cas0h -ras3/ma10 14 2 6 5 4 3 1 10 11 12 13 15 7 9 (drq3) (drq2) dselb (drq0) dsela (drq1) a0 a1 a2 e1 e2 e3 y0 y1 y2 y3 y4 y5 y6 y7 (nc) -dack7 -dack6 -dack5 -dack3 -dack2 -dack1 -dack0 1 2 3 6 5 4 15 14 13 12 11 10 9 7 * . figure 5-1. mra mode implementation system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-3
encoded ras (shared cas) this mode is the same as sra mode, except the four ras signals are encoded. an external 74f538 can than be used to decode the four signals into eight ras lines for controlling up to eight banks of dram (see figure 5-2). with the advent of 4mb drams and the 4mb modes in scatsx, there is probably no further reason to use encoded ras in new designs. in addition, the added delay on ras and cas signals (as compared to mra mode) makes 25mhz zero wait-state operation unachievable if worst-case dram specifications are to be satisfied. even at reduced speeds, the need to change the ras code when switching between memory banks adds a performance degrading t-state as compared to sra mode (two t-states as compared to mra). 2. selecting one of the ras encode mode using icr4dh-4:0. 1. enabling icr4eh-7 and encoded ras mode is enabled by: high except for refresh. or-gate causes all -ras signals to go low during refresh. vcc -dras7 -dras6 -dras5 -dras4 -dras3 -dras2 -dras1 -dras0 -ras3 -ras2 -ras1 -ras0 -refresh -xmemr 82c836 from to drams y7 y6 y5 y4 y3 y2 y1 y0 11 9 8 18 19 1 2 3 16 15 14 13 17 7 6 5 4 12 g4 g3 g2 g1 c b a oe2 oe1 al 74f538 74f32 figure 5-2. encoded ras generation n dram interface system interface 5-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
in all three modes, support is provided for 256kx1, 256kx4, 1mx1, and 1mx4 drams. in addition, mra and sra modes support 4mbx1 and 4mbx4 drams. corresponding simm modules are also supported; including 36-bit simms utilizing either dedicated cas signals or shared cas between banks (the shared-cas type cannot be used in mra mode). with 4mbx1 or 4mbx4 drams, a maximum of three banks can be supported. the ras signal for the third bank (-ras3) becomes ma10. in non-4mb configurations, the multiplexed memory address is limited to ma0-9. the usage of dreq and dack signals in sra and mra modes is summarized as follows (see figure 5-1 shown earlier): in sra mode, there are seven dreqs and seven dacks. in mra mode, two dreqs become dsel signals to control the 74f153 multiplexer, and three dreqs become cas signals. similarly, four dacks become encoded to drive the 74als138 decoder, and three dacks become cas signals. the net result is six additional cas signals as compared to sra mode. if parity checking is implemented, each bank is 18 bits wide: two data bytes, each of which has one parity bit, in addition to the data bits. parity is odd, i.e., a data byte value of ffh will have a ?? one ?? for the associated parity bit. whenever a byte or word is written, a parity bit is generated and written along with each byte. when a read occurs, the stored parity bit is compared to the parity calculated from the read byte. if a mismatch occurs during a read operation, a parity error is reported and an nmi is generated indicating a problem with memory. the nmi generation for parity errors can be disabled using bit 6 of internal configuration register 46h, or bit 2 of i/o port 61h. if the system designer decides not to implement the parity bit (because of cost or other reasons), nmi generation due to parity error should be disabled as described. for minimum system parts count, the ma, ras, cas, mwe, and par signals from the 82c836 may each drive up to 18 dram chips directly without buffering. this corresponds to two simm modules having nine dram chips per module, or 6 simm modules having three dram chips (256kx4, 1mx4, or 4mx4 drams) per module. there are two simm modules in each memory bank. since each cas line drives only one byte in each memory bank, the cas lines effectively can drive twice as many memory banks (in sra or encoded ras modes) as the ma and mwe lines. also, since each memory bank is driven by a separate ras line, ras lines do not need buffering. the parity lines (parl, parh) drive only one dram chip in each bank and should be able to drive up to eight banks without buffering. similarly, the md lines also drive only one dram chip in each bank, and the 80386sx and 80387sx are both rated for high capacitive loads. so, no buffering should be needed between md lines and the cpu local data bus in the typical system implementation. a four-bank memory and architecture consisting entirely of simms having three dram chips each (24 drams total) is a special exception to the 18-dram guideline. the load distribution in this case makes ma and mwe buffering unnecessary. system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-5
in addition to the memory address ranges for rom and shadow ram discussed earlier, local ram can be enabled or disabled in a single 384kb block in the range 040000h-09ffffh (icr 4eh). memory addresses in the range 100000h-ffffffh (extended memory) and ems access (expanded memory) are discussed in a later section titled scatsx memory bank utilization . memory accesses always go to the at bus, unless local ram or rom has been enabled at the referenced memory address. bits 4-0 of internal configuration register 4dh must be set according to the physical dram configuration. table 5-1 shows the valid configurations with either nonencoded ras or encoded ras. table 5-2 shows additional configurations that are valid only with encoded ras. table 5-3 shows the 4mb configurations, valid only with nonencoded ras. table 5-1. valid configurations ---- nonencoded or encoded ras banks ? icr 4dh bits 4-0 ? 0 1 2 3 4-7 total local memory 00h 0 0 0 0 0 0 01h 256kw 0 0 0 0 512kb 02h 256kw 256kw 0 0 0 1mb 03h a 256kw 256kw 0 0 0 640k + 384k 04h 256kw 256kw 256kw 0 0 1.5mb 05h 256kw 256kw 256kw 256kw 0 2mb 06h 256kw 256kw 1mw 0 0 3mb 07h 256kw 256kw 1mw 1mw 0 5mb 08h ? 256kw 1mw 0 0 0 2.5mb 09h ? 256kw 1mw 1mw 0 0 4.5mb 0ah ? 256kw 1mw 1mw 1mw 0 6.5mb 0bh 1mw 0 0 0 0 2mb 0ch 1mw 1mw 0 0 0 4mb 0dh 1mw 1mw 1mw 0 0 6mb 0eh ? 1mw 1mw 1mw 1mw 0 8mb k = 1024 m = 1048576 w = word (two bytes) b = byte all memory accesses go to the at bus. this can be used to turn off on-board ram even if on-board ra m exists. the dram is mapped as 1mb conventional (subject to enabling or disabling of the top 384k) and no ext ended memory. a the dram is mapped as 640kb conventional, 384kb extended. the 384kb block is addressed at 100000h-1 5ffffh. there is no shadow ram. ? in all configurations, all memory beyond the first 1mb (or beyond the first 640kb in configuration 0 3h) is available for use as extended memory (addressed linearly starting at 100000h). extended memory can be accessed either directly (in 80386sx protecte d mode) or through expanded memory address translation (ems). ? banks are normally mapped in ascending physical address order i.e., bank 1 has a higher starting add ress than bank 0, etc. however, in configuration 08-0ah, the mapping order is changed so that the 256kw bank has the highest starting address instead of the lowest. n dram interface system interface 5-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 5-2. valid configurations ---- encoded ras only banks icr 4dh bits 4-0 ? 0 and 1 2 and 3 4 5 6 7 total local memory 0fh 256kw 1mw 1mw 0 0 0 7mb 10h 256kw 1mw 1mw 1mw 0 0 9mb 11h 256kw 1mw 1mw 1mw 1mw 0 11mb 12h 256kw 1mw 1mw 1mw 1mw 1mw 13mb 13h 1mw 1mw 1mw 0 0 0 10mb 14h 1mw 1mw 1mw 1mw 0 0 12mb 15h 1mw 1mw 1mw 1mw 1mw 0 14mb 16h 1mw 1mw 1mw 1mw 1mw 1mw 16mb k = 1024 m = 1048576 w = word (two bytes) b = byte in all configurations, all memory beyond the first 1mb is available for use as extended memory (addr essed linearly starting at 100000h). extended memory can be accessed either directly (in 80386sx protected mode) or through expanded memory address trans lation (ems). ram above fc0000h is accessible only through ems. direct accesses to fc0000h-ffffffh by the cpu go to rom. table 5-3. 4mb dram configurations ---- nonencoded ras only banks icr 4dh bits 4-0 ? 0 1 2 3 4-7 total local memory 17h 256kw 256kw 4mw 0 0 9 mb 18h 1mw (or 0) 4mw 0 0 0 10 mb (or 8mb) 19h 4mw 4mw 0 0 0 16 mb k = 1024 m = 1048576 w = word (two bytes) b = byte the function of the -ras3 pin automatically changes to ma10 function whenever a 4mb dram configurati on (17h, 18h, 19h) is selected. bank 1 covers address 0-7fffffh and bank 0 begins at 800000h. consequently, bank 0 can remain empty if no internal ems accesses are performed in the bank 0 range (800000h-9fffffh), and if icr 4eh is set to 800000h top-of-ram address. the row address for the drams comes from higher-order bits of the complete physical address, while the column address comes from bits 1 through 9 for 256k drams, 1 through 10 for 1mb drams, or 1 through 11 for 4mb drams. thus, the memory addresses accessible by changing the column address only, without changing the row address, are contiguous and constitute a physical memory ?? page ?? . successive memory accesses to the same page do not require -ras to be cycled, since it is already active and the row address is already valid. this saves considerable time in memory accessing because only -cas needs to be cycled. the scatsx architecture always uses -cas only accessing (also known as page mode) whenever possible. dma, master cycles, and refresh leave -ras inactive even if the preceding and following cpu memory accesses are in the same page. system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-7
three different types of local memory cycles can occur (listed in order of increasing cycle time): page hit: -ras is already active and the row address is already valid, so only -cas needs to be cycled. ras high: -ras for the target bank is high initially, so there is no need to wait for -ras precharge time. page miss: access to the same bank, but with a different row address, so -ras must be cycled high and low before -cas timing can begin. the major difference between mra and sra modes, and the reason for implementing mra mode, is the performance improvement in bank switch cycles. ?? bank switch ?? means accessing a different dram bank than the preceding dram access. with mra mode, ras for the new bank frequently will be already active from an earlier access, so the bank switch can be performed without any delay for ras cycling. the result is a cycle equal in speed to a page hit. in contrast, sra mode forces all bank switch cycles to be ras high cycles, since ras for the new bank will always be high initially. t-state counts for these cycles are as follows: page hit read is 0ws page hit write is 1ws ras high read or write, nonencoded ras is 1ws ras high read or write, encoded ras is 2ws page miss, same bank, read or write is 3ws the total number of t-states for pipelined cycles is the ws amount plus 2; for nonpipelined cycles, ws plus 3. if ems is enabled, one further t-state is added for all cycle types for accesses that require address translation. a minimum of 2.5 t-states are always allowed for read data access from -ras (100ns at 25mhz cpu speed, 125ns at 20mhz cpu speed, 156ns at 16mhz cpu speed). this allows the use of 60ns drams at 25mhz, 80ns drams at 20mhz, or 100ns drams at 16mhz. the majority of all memory accesses are instruction fetches, which tend to cluster in short bursts of accesses in highly localized address ranges. even jump operations frequently are localized. thus, paging usually results in substantial performance improvement over nonpaged memory timing, since a high percentage of memory cycles can be -cas only. in addition to paging, four-way page interleaving is automatically performed in banks 0-3 whenever they all contain the same size dram (configurations 05h, 0eh and 13h through 16h). page interleaving means that the physical dram pages (-cas only adressable blocks) are interleaved in sequence across the four banks i.e., page n in bank 0, n+1 in bank 1, n+2 in bank 2, n+3 in bank 3, n+4 in bank 0 again, and so on. this has the effect of increasing the relative probability of bank switch cycles over page misses; resulting in significant performance improvement over simple paging without interleaving. similarly, if banks 4-7 are enabled and contain the same size drams, four-way page interleaving is automatically performed in those four banks. refer to configurations 12h and 16h in table 5-2 (shown earlier). n dram interface system interface 5-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
if any two bank pairs are of the same size, but the other pair is empty or has only one bank populated, then two-way page interleaving is automatically performed in the two same-size banks. the banks are paired as follows: 0 and 1, 2 and 3, 4 and 5, 6 and 7. in addition, banks 1 and 2 are two-way page interleaved in configurations 09h and 0ah, with noninterleaved page mode in the remaining banks. thus, the only configurations in which no interleaving occurs are 00h, 01h, 08h, 0bh, and 18h. a ras timeout feature is provided to support drams requiring a 10 microsecond maximum ras-active time. if the timeout is enabled, ras is not allowed to remain low continuously for more than about 9.5 microsecond. if the timeout is disabled, periodic refresh cycles limit the maximum possible ras active time to about 15 microseconds. scatsx memory address mapping modes the following table summarizes how cpu address bits are mapped into dram row and column address bits and which bits determine bank selection. the ?? r ?? bits do not necessarily map in an exact one-to-one bit order, but the r bits as a group do correspond to the cpu address bits indicated. ?? page size ?? refers to the block size accessible by changing column address bits only. table 5-4. memory address mapping modes cpu address bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 page size 4mw, 2-way r r r r r r r r r r r * c c c c c c c c c c c ---- 4kb 4mw, page only ---- r r r r r r r r r r r c c c c c c c c c c c ---- 4kb 1mw, 4-way ---- r r r r r r r r r r * * c c c c c c c c c c ---- 2kb 1mw, 2-way ---- ---- r r r r r r r r r r * c c c c c c c c c c ---- 2kb 1mw, page only ---- ---- ---- r r r r r r r r r r c c c c c c c c c c ---- 2kb 256kw, 4-way ---- ---- ---- r r r r r r r r r * * c c c c c c c c c ---- 1kb 256kw, 2-way ---- ---- ---- ---- r r r r r r r r r * c c c c c c c c c ---- 1kb 256kw, page only ---- ---- ---- ---- ---- r r r r r r r r r c c c c c c c c c ---- 1kb r = row address bit c = column address bit * = bank select bit for interleaving ---- = high level decoding and byte selection w = word (even and odd bytes) system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-9
scatsx memory bank utilization the following tables summarize the exact address ranges and interleaving sequences for each supported memory configuration. it is assumed that shadow ram is enabled, internal ems is disabled, and the top of ram (icr 4e) is set to the entire on-board memory. table 5-5. memory configuration address ranges and interleaving sequences physical configuration address ranges map mode banks page interleave size 00 = no on-board dram none ---- ---- ---- 01 = 2x256kb 000000-07ffffh 256kw/p 0 ---- 02 = 4x256kb (1m/0) 000000-0fffffh 256kw/2wi 0, 1 400h 03 = 4x256kb (640/384) 000000-09ffffh 256kw/2wi 0, 1 400h 03 = 4x256kb (640/384) 100000-15ffffh 256kw/2wi 0, 1 400h 04 = 6x256kb 000000-0fffffh 256kw/2wi 0, 1 400h 04 = 6x256kb 100000-17ffffh 256kw/p 2 ---- 05 = 8x256kb 000000-1fffffh 256kw/4wi 0-3 400h 06 = 4x256kb, 2x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 06 = 4x256kb, 2x1mb 100000-2fffffh 1mw/p 2 ---- 07 = 4x256kb, 4x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 07 = 4x256kb, 4x1mb 100000-4fffffh 1mw/2wi 2, 3 800h 08 = 2x256kb, 2x1mb 000000-1fffffh 1mw/p 1 ---- 08 = 2x256kb, 2x1mb 200000-27ffffh 256kw/p 0 ---- 09 = 2x256kb, 4x1mb 000000-3fffffh 1mw/2wi 1, 2 800h 09 = 2x256kb, 4x1mb 400000-47ffffh 256kw/p 0 ---- 0a = 2x256kb, 6x1mb 000000-3fffffh 1mw/2wi 1, 2 800h 0a = 2x256kb, 6x1mb 400000-5fffffh 1mw/p 3 ---- 0a = 2x256kb, 6x1mb 600000-67ffffh 256kw/p 0 ---- 0b = 2x1mb 000000-1fffffh 1mw/p 0 ---- 0c = 4x1mb 000000-3fffffh 1mw/2wi 0, 1 800h 0d = 6x1mb 000000-3fffffh 1mw/2wi 0, 1 800h 0d = 6x1mb 400000-5fffffh 1mw/p 2 ---- 0e = 8x1mb 000000-7fffffh 1mw/4wi 0-3 800h n dram interface system interface 5-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 5-6. memory configuration address ranges and interleaving sequences encoded ras only physical configuration address ranges map mode banks page interleave size 0f = 4x256kb, 6x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 0f = 4x256kb, 6x1mb 100000-4fffffh 1mw/2wi 2, 3 800h 0f = 4x256kb, 6x1mb 500000-6fffffh 1mw/p 4 ---- 10 = 4x256kb, 8x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 10 = 4x256kb, 8x1mb 100000-4fffffh 1mw/2wi 2, 3 800h 10 = 4x256kb, 8x1mb 500000-8fffffh 1mw/2wi 4, 5 800h 11 = 4x256kb, 10x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 11 = 4x256kb, 10x1mb 100000-4fffffh 1mw/2wi 2, 3 800h 11 = 4x256kb, 10x1mb 500000-8fffffh 1mw/2wi 4, 5 800h 11 = 4x256kb, 10x1mb 900000-afffffh 1mw/p 6 ---- 12 = 4x256kb, 12x1mb 000000-0fffffh 256kw/2wi 0, 1 400h 12 = 4x256kb, 12x1mb 100000-4fffffh 1mw/2wi 2, 3 800h 12 = 4x256kb, 12x1mb 500000-cfffffh 1mw/4wi 4-7 800h 13 = 10x1mb 000000-7fffffh 1mw/4wi 0-3 800h 13 = 10x1mb 800000-9fffffh 1mw/p 4 ---- 14 = 12x1mb 000000-7fffffh 1mw/4wi 0-3 800h 14 = 12x1mb 800000-bfffffh 1mw/2wi 4, 5 800h 15 = 14x1mb 000000-7fffffh 1mw/4wi 0-3 800h 15 = 14x1mb 800000-bfffffh 1mw/2wi 4, 5 800h 15 = 14x1mb c00000-dfffffh 1mw/p 6 ---- 16 = 16x1mb 000000-7fffffh 1mw/4wi 0-3 800h 16 = 16x1mb 800000-ffffffh* 1mw/4wi 4-7 800h * top 128kb or 256kb accessible only via ems. table 5-7. memory configuration address ranges and interleaving sequences nonencoded ras only physical configuration address ranges map mode banks page interleave size 17 = 4x256kb, 2x4mb 000000-0fffffh 256kw/2wi 0, 1 400h 17 = 4x256kb, 2x4mb 100000-8fffffh 4mw/p 2 ---- 18 = 2x1mb, 2x4mb 000000-7fffffh 4mw/p 1 ---- 18 = 2x1mb, 2x4mb 800000-9fffffh 1mw/p 0 ---- 19 = 4x4mb 000000-ffffffh* 4mw/2wi 0, 1 1000h * top 128kb or 256kb accessible only via ems. system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-11
automatic memory configuration detection typical system bios implementations include automatic tests to determine memory mode and configuration without requiring user intervention. the following operational characteristics may be useful for these bios algorithims: external hardware can be encoded ras (sra), nonencoded ras (sra), or mra. encoded ras hardware can be detected by testing bank 0 in both encoded ras and nonencoded ras (sra) modes. bank 0 is inaccessible in sra mode if the external hardware is encoded ras, but is accessible in either sra or mra mode with nonencoded ras hardware. if encoded ras hardware is detected, configuration 16h (8 banks of 1mw) can be used to detect 256k or 1mb dram size. if address bit 10 is ignored, i.e., the same physical data is accessible regardless of a10, then the dram is 256k. address bit 10 corresponds to an address increment of 400h. with nonencoded ras hardware, bank 1 (if not empty) can be used to detect mra or sra hardware. if the external hardware is mra, but sra mode is used, or vice versa, bank 1 is inaccessible. however, if bank 1 is empty, there is probably no simple way to differentiate between sra and mra. schemes involving dma requests are possible but probably are not general enough to work in all possible system configurations (mra or sra mode must still be setup correctly for the dma channels to operate properly). 256k dram size can be detected in banks 0-3 using configuration code 0eh (4 banks of 1mw). if address bit 10 is ignored, i.e., same memory data accessed regardless of a10, then the dram is 256k. address bit 10 corresponds to an address increment of 400h. if bank 3 is empty and 256kw has been found in banks 0 and 1, then bank 2 can be tested for 4mw using configuration 17h. otherwise, if banks 2 and 3 are both empty, then banks 0 and 1 can be tested for 4mw using configuration 19h. in either case, address bit 11 being ignored indicates 1mb dram size. address bit 11 corresponds to an address increment of 800h. support for external cache further system performance improvement can be achieved by implementing an external cache. typical caches operate by ?? remembering ?? a group of addresses and the data that was last written at each address. when the same address is subsequently read back, the cache provides the read data at a very high speed. the remembered addresses are generally referred to as ?? tag ?? addresses. a ?? cache read hit ?? refers to a read cycle in which the read address matches a previously stored tag address, so the valid read data can be provided by the cache instead of the addressed system resource. a ?? cache write hit ?? refers to a write cycle in which the write address matches a stored tag address, so the associated data for that tag address must either be updated or marked as invalid. a ?? cache miss ?? refers to a read or write cycle in which the read or write address does not match any stored tag addresses. the cache can either ignore the ?? miss ?? cycle or ?? remember ?? the new tag address and associated data. n dram interface system interface 5-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
a fundamental assumption of cache systems is that the read data remains the same on successive reads until subsequently rewritten. this will always be true for memory read operations (unless address remapping is occurring, and particular addresses don?t necessarily remain mapped to the same physical memory locations). it is also possible to cache i/o cycles as long as the basic ?? data constancy ?? assumption is satisfied. typical cache schemes may differ radically from each other in the exact strategy they use for deciding when to update the cache and how to organize the stored tags. the 82c836 provides the following features for external cache support: three configuration bits in icr41h allow optional enabling of early ready mode, local bus access (lba) mode, and/or force bus convert mode. the early ready mode allows an external cache to claim a nonpipelined, cpu-generated, cycle by asserting -ready during the first t2 state. the 82c836 does not generate a cycle in this case, and relies on the external cache to provide the read data or accept the write data. the result is a two t-state cycle (t1-t2). lba mode is essentially the same as early ready, except the -0ws input is used instead of -ready as the cache hit signal, and -ready generation is left entirely to the external cache controller or other external source. this allows cache implementations in which -ready needs to be delayed. with an external gate or multiplexer, the -0ws signal can still be used as a normal at bus -0ws input even when lba mode is enabled. the -lba and at bus -0ws signals can simply be anded together (i.e., low-true or) to provide the -lba/-0ws input to the 82c836. to allow cache implementations to cache 16 bits at a time and also cache at bus accesses, the force bus convert mode can be used to force all at bus reads to be 16 bits, including reads from 8-bit memory or i/o resources. reads from local dram are always 16 bits automatically, regardless of force bus convert mode. to avoid a performance penalty when using 8-bit at bus memory resources such as 8-bit video memory, the force bus convert feature does not apply to at bus memory resources residing in the first 1mb of address space. external devices, such as a cache controller, may need a cpu cycle start signal if they do not monitor -ads and -ready directly. to provide such a signal, the -na pin function can be changed by the -dack3 strap option to operate as a start cycle (-stcyc) signal instead of a next address (-na) signal. the signal can still be used as a 74f543 address latch enable, if desired, in either case. the following types of cpu generated cycles can be ?? claimed ?? by using the early ready or lba mode: local dram reads, but not local dram writes; local dram writes can be claimed also, if icr 63h bit 0 is set. one use for this feature is directly reading and writing cache data ram in a diagnostic test. at bus memory reads or writes, i/o reads or writes, and interrupt acknowledge. when using early ready or lba modes, the cpu -na input must be tied high, causing the cpu to operate in nonpipelined mode only. this is necessary because of cpu address timing. the 82c836 may need to generate a local dram cycle if the cycle is not claimed by an external controller, and the 82c836 requires valid cpu address beyond the point at which it could change in a pipelined cycle. system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-13
if either lba or early ready mode is enabled (or both), the 82c836 automatically generates an early wait state at the beginning of every local dram read cycle not claimed by an external controller. this allows time for the external controller to signal a cache hit before the 82c836 starts a dram cycle. the added wait state affects the total cycle time only in the event of a cache read miss. cache read hits can be zero wait state if the external cache controller uses early ready mode. there is no added wait state for local dram write cycles. to avoid the need for parity bits in the cache srams, parity checking on local dram read cycles is suspended in the event of a cache hit. parity checking of local dram memory operates normally on cache misses. when using both local memory caching and internal ems, the ems page windows and ems target areas (expanded memory) must be excluded from the cacheable address ranges. since ems address translation is entirely internal to the 82c836, a local memory cache only has access to cpu addresses, not translated ems addresses. expanded/extended memory the 82c836 fully supports the lim ems 4.0 and 3.2 specifications. ems allows operating systems and software applications to access memory above the 1mb dos limit through a page mapping scheme managed by an ems driver. the scatsx architecture allows up to 64kb of address space in the first 1mb to be remapped, in 16kb pages, to anywhere in the 16mb address space, described as follows: remappable area ---- the remappable address range is either 0d0000-0dffffh or 0e0000-0effffh, determined by a bit in one of the ems i/o ports (see below). in lim ems terminology, this 64kb remappable address range is referred to as the page frame. page windows and target pages ---- the remappable address range is divided into four page windows of 16kb each. each page window can be mapped to any 16kb target page anywhere in the 16mb address space. in lim ems terminology, the page windows are referred to as physical pages because these have fixed physical addresses. the target pages are referred to as logical pages because these have logical addresses only ---- until mapped into a physical page within the page frame. page registers ---- associated with each page window is a page register. the 82c836 contains four page registers, one for each 16kb page window. each page register specifies the absolute physical location of the 16kb target page to be mapped into the associated page window. each page register also specifies whether or not the associated page window is enabled or disabled, i.e., whether or not to perform ems address remapping in that window. if a page window is disabled, accesses to that window are treated as ordinary non-ems memory accesses. ems i/o ports ---- the page registers are accessed using three i/o ports located at either i/o addresses 208h-20ah or 218h-21ah (selectable via icr 4f bit 0). in i/o port 20ah (or 21ah), bits 1-0 specify which page register is currently accessible. the selected page register is then accessed at i/o ports 208h and 209h (or 218h and 219h). ems enable/disable ---- ems translation can be enabled or disabled by icr 4f bit 7. in addition, the ems i/o ports can be enabled or disabled by icr 4f bit 6. n dram interface system interface 5-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
the target pages can come from anywhere in system memory, including the first 1mb. no hardware checking is performed for conflicts with dos memory or other memory areas. it is the responsibility of the ems driver to select appropriate values for the page register contents. to avoid potential conflicts between extended memory and ems memory, i.e., software erroneously altering ems memory through extended memory access, internal configuration register 4e, bits 3-0, can be used to set a limit on the top of extended memory. memory above that limit will then be accessible only through the ems mechanism. direct cpu memory accesses at addresses above the limit will go to the at bus see figure 5-3. ems paging and the ems i/o ports are normally managed by application software or an ems driver that allows applications to access more ram than is normally allowed by dos. more information on software implementation can be obtained from various intel a and microsoft a publications. icr 4d,4:0 = 0101, 2m memory only ems access allowed both cpu access and ems access allowed icr 4e,2:0 = 011 , 1.5m extended boundary space "dos" ems windows memory expanded 2m 1.5m 1m 640k 0 1 1 2 2 memory extended figure 5-3. example of ems/extended memory system interface dram interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-15
numeric coprocessor interface the 82c836 contains interface logic that supports use of an 80387sx numeric coprocessor. the logic provides the following features: precisely times the system reset signal (xrst) to properly synchronize the 80387sx internal phase clock. due to pin limitations, the 82c836 does not provide a separate coprocessor reset signal and does not support coprocessor reset via output to port f1h. an output to f1h is invaraiably followed by an finit instruction, which is sufficient to insure a full reset of the coprocessor. (finit alone is not sufficient for an 80287 because of protected mode, but the 80387sx does not differentiate between protected and real modes.) automatically detects the presence or absence of the 80387sx by sensing the coprocessor -error signal during system reset (xrst). detects and latches coprocessor error status. generates an interrupt (irq13) to the system when an error occurs, and keeps -busy to the cpu active until error processing has begun, as indicated by an i/o write to port f0h. (as in all at-compatible architectures, the -error input to the cpu is not used.) generates -ready to the cpu if desired or, optionally, relies on the 80387sx to generate -ready. in order for the 80387sx to generate -ready, an external three-state inteface, such as that shown in figure 5-4, is needed between 80387sx -readyo and 80386sx -ready. if the 82c836 is programmed to generate -ready during coprocessor accesses, the 80387sx -readyo output should be left open and the external -readyo interface is unnecessary. generates a dummy -busy signal to the cpu when no coprocessor is present (for compatibility with software packages using certain critical coprocessor instructions to test for coprocessor presence). the dummy -busy signal is just a buffered, inverted version of -refresh. n numeric coprocessor interface system interface 5-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
additional considerations are as follows: whenever a coprocessor error has occurred and the coprocessor is not busy, external logic should force pereq to the 80386sx active (high) to allow the 80386sx to finish any remaining i/o cycles in the current (error causing) coprocessor instruction. this mode, forcing pereq when the coprocessor is not busy, should end as soon as the 80386sx acknowledges the coprocessor error condition, as indicated by the 82c836 -busy output going inactive. a circuit for accomplishing this is shown in the system schematics. due to pin limitations, it was not possible to incorporate this logic inside the 82c836. certain software packages are known to rely on reading coprocessor status to determine coprocessor presence or absence. to guarantee that coprocessor status will be invalid in the event that no coprocessor is preset, a low-order data bit, such as d0, should be pulled down instead of pulled up (see appendix a, system schematics ). (for delayed -ready turnoff on rising edge of -readyo) time delay (to 80386sx) -ready 74f125 74f125 74f125 74f125 (from 80387sx) -readyo figure 5-4. -readyo interface system interface numeric coprocessor interface n chips and technologies, inc. p r e l i m i n a r y revision 3.0 5-17
keyboard controller interface ---- external 8042 the 82c836 relies on an external 8042 to handle keyboard operations (see figure 5-5). the clock for the 8042 may be derived from busclk or osc and should have a frequency between 6mhz and 10mhz when used with standard keyboard controllers. the 8042 interfaces with the 82c836 through irq1 and a chip select line. the 8042 also provides two output signals: gatea20 and -reset2. these signals are brought into the 82c836 and combined internally with the fast gate a20 and fast cpu reset functions available via port 92h. the keyboard controller also supports the keylock and cga strap functions. figure 5-5. keyboard controller n keyboard controller interface ---- external 8042 system interface 5-18 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 6 real time clock and interval timer registers real time clock interface ---- mc146818 compatible the 82c836 contains an internal, mc146818-compatible real time clock (rtc) with a total of 128 bytes of cmos ram (including the dedicated bytes used for clock functions). the internal rtc may be disabled so that an external rtc can be used. internal/external rtc mode is selected by the state of the -extrtc signal (-dack5) during power-up. if this pin is pulled low with a 4.7k ohm resistor, external rtc mode is selected. a 4.7k ohm pull-up resistor puts the 82c836 into internal rtc mode. when the internal rtc is used: 82c836 vcc pins should be connected to battery-backed power mfp4 is used as the 32khz clock input mfp5 is used as the power sense input. when an external rtc is used: 82c836 vcc pins should be connected to the normal power source mfp4 is used as the irq8 input from the rtc mfp5 is used as the rtccs- chip select output for the rtc -rtccs should be connected to pwrgood through a diode (see figure 3-2 shown earlier). the internal rtc combines a complete time-of-day clock with alarm, one hundred year calendar, a programmable periodic interrupt, and 114 bytes of low-power static ram. provisions are made to enable the device to operate in a low-power (battery powered) mode and protect the contents of both the ram and clock during system power-down. chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-1
register access table 6-1 shows the address map for the real time clock. table 6-1. address map for the real time clock column function column function 00 seconds 09 year 01 seconds alarm 0a register a 02 minutes 0b register b 03 minutes alarm 0c register c 04 hours 0d register c 05 hours alarm 0e register d 06 day of the week 0f user ram 07 day of the month 10-7f user ram 08 month i/o ports 70h and 71h are used for accessing the 128 locations in the real time clock. first the index address (0 to 7fh) is output to port 70h, then the data is read or written at port 71h. the entire port 70h/71h sequence should be completed while interrupts are inhibited, or during an interrupt service routine before re-enabling interrupts. otherwise, an interrupt service routine could potentially intervene between the output to port 70h and the subsequent i/o to port 71h, overwriting the port 70h value. real time clock address map table 6-1 (shown above) identifies the internal register/ram organization of the real time clock portion of the 82c836. the 128 addressable locations in the real time clock are divided into ten bytes that normally contain the time, calendar and alarm data, four control and status bytes, and 114 general pupose ram bytes. all 128 bytes are readable by the cpu. the cpu may also write to all locations except registers c, d, bit 7 of register a, and bit 7 of the seconds byte, which is always zero. time calendar and alarm bytes the cpu can obtain the time and calendar information by reading the appropriate locations in the real time clock. initialization of the time, calendar, and alarm infomration is accomplished by writing to these locations. information is stored in these locations in binary-coded decimal (bcd) format. before initialization of the internal register can be performed, the set bit in register b should be set to a one to prevent real time clock updates from occuring. the cpu then initializes the first ten locations in bcd format. the set bit should then be cleared to allow updates. once initialized and enabled, the real time clock performs clock/calendar updates at a 1hz rate. n real time clock interface ---- mc146818 compatible real time clock and internal timer registers 6-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 6-2. format for clock, calendar, and alarm data index register address function bcd range 0 seconds 00-59 1 seconds alarm 00-59 2 minutes 00-59 3 minutes alarm 00-59 4 hours (12 hour mode) 01-12 (am), 81-92 (pm) hours (24 hour mode) 00-23 5 hours alarm (12 hour mode) 01-12 (am), 81-92 (pm) hours alarm (24 hour mode) 00-23 6 day of week 01-07 7 day of month 01-31 8 month 01-12 9 year 00-99 table 6-2 above shows the format for the ten clock, calendar, and alarm data. the 24/12 bit in register b determines whether the hour locations are updated using a 1-12 or 0-23 format. in 12 hour format, the high order bit of the hours byte in both the time and alarm bytes indicates pm when it is set to one. during uptdates, which occur once per second, the ten bytes of time, calendar, and alarm information are unavailable to be read or written by the cpu for a period of 2ms. these ten locations cannot be written to during this time. information read while the real time clock is performing update is undefined. the update cycle section describes how update cycle/pcu contention problems can be avoided. the alarm bytes can be programmed to generate an interrupt at a specific time or they can be programmed to generate a peroidic interrupt. static ram the 114 bytes of ram for index address 0eh to 7fh are not affected by the real time clock. these bytes are accessible during the update cycle and may be used for whatever the designer wishes. typical applications use this as nonvolatile storage for configuration and calibration parameters since this device is normally battery powered when the system is turned off. real time clock and internal timer registers real time clock interface ---- mc146818 compatible n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-3
control and status registers the 82c836 contains four registers to control the operation and monitor the status of the real time clock. these registers are located at index address 0ah-0dh and are accessible by the cpu at all times b7 b6 b5 b4 b3 b2 b1 b0 ________ ___________________________ ____________________________________ rs periodic interrupt rate dv divider prescaler uip update in progress bits: b0-b3 rs these bits control the periodic interrupt rate. the periodic interrupt is derived from the divider/prescaler in the real time clock and is separate from the alarm interrupt. both the alarm and periodic interrupts use the same interrupt channel in the interrupt controller. use of the periodic interrupt allows the generation of interrupt rates higher than one per second. below are the interrupt rates for which the real time clock may be programmed. rate selection time base rs3 rs2 rs1 rs0 4.194304mhz or 1.048576mhz 32.768khz 0 0 0 0 none none 0 0 0 1 30.517 m s 3.90526ms 0 0 1 0 61.035 m s 7.8125ms 0 0 1 1 122.070 m s 122.070 m s 0 1 0 0 244.141 m s 244.141 m s 0 1 0 1 488.281 m s 488.281 m s 0 1 1 0 976.562 m s 976.562 m s 0 1 1 1 1.953125ms 1.953125ms 1 0 0 0 3.90625ms 3.90625ms 1 0 0 1 7.8125ms 7.8125ms 1 0 1 0 15.625ms 15.625ms 1 0 1 1 31.25ms 31.25ms 1 1 0 0 62.5ms 62.5ms 1 1 0 1 125ms 125ms 1 1 1 0 250ms 250ms 1 1 1 1 500ms 500ms figure 6-1. register a ---- address 0ah (all bits except uip are read/write) n control and status registers real time clock and internal timer registers 6-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
b7 uip update in progress flag is a status bit used to indicate when an update cycle is about to take place. a one indicates an update cycle is taking place or is imminent. uip goes active (high) 244 m s prior to the start of an update cycle and remains active for an additional 2 ms while the update is taking place. the uip bit is read only and is not affected by reset. writing a one to the set bit in register b inhibits any update cycle and then clears the uip status bit. b4-b6 dv these bits control the divider prescaler on the real time clock. while the 82c836 rtc can operate at frequencies higher than 32.768khz, this is not recommended for battery-powered operation due to the increased power consumption at these frequencies. osci frequencies and modes are: 4.194304mhz in operate mode when dv2 = 0, dv1 = 0 and dv0 = 0 1.048576mhz in operate mode when dv2 = 0, dv1 = 0 and dv0 = 1 32.768khz in operate mode when dv2 = 0, dv1 = 1 and dv0 = 0 the divider is reset when dv2 = 1 and dv1 = 1, regardless of dv0. b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ ________ ________ ________________ ________ ________ dse daylight savings enable 24/12 24-hour mode 0 uie update-ended interrupt enable aie alarm interrupt enable pie periodic interrupt enable set update cycle enable bits: b0 dse the real time clock can be instructed to handle daylight savings time changes by setting this bit to a one. this enables two exceptions to the normal time-keeping sequence to occur. setting this bit to zero disables the execution of these two exceptions. b1 24/12 the 24/12 control bit is used to establish the format of both the hours and hours alarm bytes. if this bit is a one, the real time clock interprets and updates the information in these two bytes using the 24-hour mode. this bit can be read or written to by the cpu and is not affected by reset. b2-b3 0 read as zeros. figure 6-2. register b ---- address 0bh (read only) real time clock and internal timer registers control and status registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-5
b4 uie the update-ended interrupt enable bit enables the uf (update end flag) bit in register c to assert interrupt request. this bit is cleared to a zero by reset. b5 aie the generation of alarm interrupts is enabled by setting this bit to a one. once this bit is enabled, the real time clock generates an alarm whenever a match occurs between the programmed alarm and clock information. if the ?? don?t care ?? condition is programmed into one or more of the alarm registers, this enables the generation of periodic interrupts at rates of one second or greater. this bit is cleared to a zero by reset. b6 pie the periodic interrupt enable bit controls the generation of interrupts based on the value programmed into bits b3-b0 of register a. this allows the user to disable this function without affecting the programmed rate. writing a one to this bit enables the generation of periodic interrupts. this bit is cleared to a zero by reset. b7 set writing a zero to this bit enables the update cycle and allows the real time clock to function normally. when set to one, the update cycle is inhibited and any cycle in progress is aborted. the set bit is not affected by the reset input pin. b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ ________ ________ __________________________________ 0 uf update-ended flag af alarm flag pf periodic interrupt flag irqf interrupt request flag bits: b0-b3 read as zeros. b4 uf the update-ended flag bit is set after each cycle. when the uie bit is a one, the one in uf causes the irqf bit to be a one asserting irq. uf is cleared by a register read or by a reset. b5 af a one appears in the alarmflag bit whenever a match has occurred between the time register and alarm register during an update cycle. this flag is also independent of its enable (aie) and generates an interrupt if aie is true. b6 pf the periodic interrupt flag is set to one when a transition, selected by rs3-rs0, occurs in the divider chain. this bit becomes active independent of the condition of the pie control bit. the pf bit then generates an interrupt and sets irqf if pie is one. figure 6-3. register c ---- address 0ch (read only) n control and status registers real time clock and internal timer registers 6-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
b7 irqf the interrupt request flag is set to one when any of the conditions that can cause an interrupt is true and the interrupt enable for that condition is true. the condition that causes this bit to be set also generates an interrupt. the logical expression for this flag is: irqf = pf & pie + af & aie + uf & uie this bit and all other active bits in this register are cleared by reading this register or by activation the -ps input pin. writing to this register has no effect on the contents. b7 b6 b5 b4 b3 b2 b1 b0 ________ ________________________________________________________________ 0 vrt valid ram and time bits: b0-b6 0 read as zeros. b7 vrt the valid ram and time bit indicates the condition of the contents of the real time clock. this bit is cleared to a zero whenever the ps input pin is low. this pin is normally derived from the power supply, which supplies vcc to the device and allows the user to determine whether the registers have been intialized since power was applied to the device. pwrgood has no effect on this bit, and it can only be set by reading register d. all unused register bits will be zero when read and are not writeable. update cycle during normal operation, the real time clock performs an update cycle once every second. the performance of an update cycle is contigent upon the divider bits dv<0:2> not being cleared. the function of the update cycle is to increment the clock/calendar registers and compare them to the alarm registers. if a match occurs between the two sets of register, an alarm is issued. an interrupt is issued if the alarm and interrupt control bits are enabled. while an update is taking place, the lower ten registers are unavailable to the cpu. this is done to prevent the possible corruption of data in the register or the reading of incorrect data. to avoid contention problems between the real time clock and the cpu, a flag is provided in register a to alert the user of an impending update cycle. this update in process (uip) bit is asserted 244 m s before the actual start of the cycle figure 6-4. register d ---- address 0dh (read only) real time clock and internal timer registers update cycle n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-7
and is maintained until the cycle is complete. once the cycle is complete, the uip bit is cleared and the update flag (uf) in register c is set. figure 6-5 illustrates the update cycle. cpu access is always allowed to register a through d during update cycles. two methods for reading and writing to the real time clock are recommended. both of these methods allow the user to avoid contention between the cpu and the real time clock for access to the time and date information. the first method is to read register a, determine the state of the uip bit. if the uip is zero, perform the read or write opertation. for this method to work successfully, the entire read or write operation (including any interrupt service routines which might occur) must not require more than 244 m s to complete from the beginning of the read of register a to the completion of the last read or write operation to the clock calendar registers. the second method of accessing the lower ten registers is to read register c once and disregard the contents. continue reading this register until the uf bit is a one. this bit becomes true immediately after an update is completed. the user then has until the start of the next update cycle to comlete a read or write operation. figure 6-5. update cycle n update cycle real time clock and internal timer registers 6-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
programmable interval timer ---- 8254 compatible the programmable interval timer, which is equivalent to the intel 8254 programmable interval timer/counter, is programmable through external i/o ports 0040h through 0043h (refer to figure 6-6). the inputs of the three channels are connected to a 1.19mhz clock. the 1.19mhz clock is internally generated by dividing osc1 (14.31818mhz) by 12. the output of the three channels are as follows: channel 0 is a general purpose and software interrupt timer. the output of this channel is connected to the irq0 pin of the internal programmable interrupt controller. the output of channel 1 is used internally by the 82c836 to generate refresh requests. the output of channel 2 supports tone generation for the audio speaker. the counter/timer (ctc) in the 82c836 is general purpose, and can be used to generate accurate time delays under software control. the ctc contains three 16-bit counters (counter 0-2) that can be programmed to count in binary or binary coded decimal (bcd). each counter operates independently of the other two and can be programmed for operation as a timer or a counter. all three counters are controlled from a common set of control logic. the control logic decodes control information written to the ctc and provides the controls necessary to load, read, configure, and control each counter. counter 0 and counter 1 can be port 61h bit 0 tone-generation refresh-request irq0 out1 out0 out2 out2 clk2 gate2 clk1 gate1 clk0 gate0 vcc (1.19mhz) tmrclk note: all signals shown here are internal to the 82c836. figure 6-6. programmable timer control real time clock and internal timer registers programmable interval timer ---- 8254 compatible n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-9
programmed for all six modes, but mode 1 and mode 5 have limited usefulness due the the lack of an external hardware trigger signal. counter 2 can be operated in any of six modes listed as follows. mode 0 ---- interrupt on terminal count mode 1 ---- hardware retriggerable one-shot mode 2 ---- rate generator mode 3 ---- square wave generator mode 4 ---- software triggered strobe mode 5 ---- hardware re-triggeralbe strobe all three counters in the ctc are driven from a common clock tmrclk (1.19mhz) derived by dividing osc1 (14.31818mhz) by 12. counter zero output (out0) is connected to irq0 of intc1 (see section 7, interrupt controller ) and may be used as an interrupt to the system for time keeping and task switching. counter 1 is programmed to generate pulses for use by the refresh generator. the third counter (counter 2) is a full function counter/timer. this channel can be used as an interval timer, a counter, or as a gated rate/pulse generator (normally used as a speaker tone generator). counter description each counter in the ctc contains a control register, a status register, a 16-bit counting element (ce), a pair of 8-bit counter input latches (cil and cih), and a pair of 8-bit counter output latches (col and coh). each counter also has a clock input for loading and decrementing the ce, a mode defined gate input for controlling the counter (only gate2 is controlled by i/o port 61h, bit 0), and an out signal. the out signal?s state and function are controlled by the counter mode and condition of the ce. the control register stores the mode and command information used to control the counter. the control register may be loaded by writing a byte, containing a pointer to the desired counter, to the write control word address (043h). the remaining bits in the byte contain the mode, type of command, and count format information. the status register allows the software to monitor counter condition and read back the contents of the control register. the counting element is a loadable 16-bit synchronous down-counter. the ce is loaded or decremented on the falling edge of tmrclk. the ce contains the maximum count when a zero is loaded; this is equivalent to 65536 in binary operation or 10000 in bcd. the ce does not stop when it reaches zero. in modes 2 and 3, the ce is reloaded. in all other modes it wraps around to ffffh in binary operation or 9999 in bcd. the ce is indirectly loaded by writing one or two bytes (optional) to the counter input latches which are in turn loaded into the ce. this allows the ce to be loaded or reloaded in one tmrclk cycle. the ce is also read, indirectly, by reading the contents of the counter output latches. col and coh are transparent latches that can be read while transparent or latched. n counter description real time clock and internal timer registers 6-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
programming the counter timer controller after power-up, the conditions of the ctc control register, counter register, ce, and the output of all counters is undefined. each counter must be programmed before it can be used. counters are programmed by writing a control word and then an initial count. the control register of a counter is written to by writing to the control word address, as shown in table 6-3. figure 6-7 shows the control word structure. the control word is a write-only location. table 6-3. counter timer control i/o addresses address function address function 040h counter 0 read/write 042h counter 2 read/write 041h counter 1 read/write 043h control word, write only b7 b6 b5 b4 b3 b2 b1 b0 ___________________________________ __________________________ ________ bcd binary coded decimal m<0:2> counter mode f<0:3> command flag bits: b0 bcd bcd selects binary coded decimal counting format during read/write counter commands. when bit 0 is set to zero, the count is binary; when bit 0 is set to one, the count is bcd. note that during read-back command, this bit must be zero. b1-b3 m<0:3> these three bits determine the counter?s mode during read/write counter commands, or select the counter during a read-back command. bits 1-3 become ?? do not care ?? during latch counter commands. figure 6-7. control word ---- address 043h real time clock and internal timer registers programming the counter timer controller n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-11
b4-b7 f<0:3> these four bits determine the command to be performed as shown below. f3 f2 f1 f0 command 0 0 0 0 latch counter 0 (see counter latch command) 0 0 0 1 read/write counter 0 lsb only 0 0 1 0 read/write counter 0 msb only 0 0 1 1 read/write counter 0 lsb then msb 0 1 0 0 latch counter 2 (see counter latch command) 0 1 0 1 read/write counter 1 lsb only 0 1 1 0 read/write counter 1 msb only 0 1 1 1 read/write counter 1 lsb then msb 1 0 0 0 latch counter 2 (see counter latch command) 1 0 0 1 read/write counter 2 lsb only 1 0 1 0 read/write counter 2 msb only 1 0 1 1 read/write counter 2 lsb then msb 1 1 x x read-back command (see counter read-back command) msb = most significant byte lsb = least significant byte x = don?t care read/write counter command when writing to a counter, two convensions must be observed: each counter?s control word must be written before the initial count is written. writing the initial count must follow the format specified in the control word (least significant byte only, most significant byte only; or least significant byte, then most significant byte). a new initial count can be written into the counter any time after programming without rewriting the control word, as long as the programmed format is observed. during read/write counter commands m<2:0> are defined as follows: select mode 0 when m2 = 0 and m1 = 0 and m0 = 0 select mode 1 when m2 = 0 and m1 = 0 and m0 = 1 select mode 2 when m1 = 1 and m0 = 0 (m2 is ?? don?t care ?? ) select mode 3 when m1 = 1 and m0 = 1 (m2 is ?? don?t care ?? ) select mode 4 when m2 = 1 and m1 = 0 and m0 = 0 select mode 5 when m2 = 1 and m1 = 0 and m0 = 1 n programming the counter timer controller real time clock and internal timer registers 6-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
latch counter command when a latch counter command is issued, the counter?s output latches (col and coh) latch the current state of the ce. col and coh remain latched until read by the cpu, or the counter is reprogrammed. the output latches then return to a ?? transparent ?? condition. in this condition, the latches are enabled and the contents of the ce may be read directly. latch counter commands may be issued to more than one counter before reading the first counter to which the command was issued. also, multiple latch counter commands issued to the same counter without reading the counter cause all but the first command to be ignored. read-back command the read-back command allows the user to check the count value, mode, and state of the out signal and null count (nc) flag of the selected counter(s). the format of the read-back command is shown in figure 6-8. b7 b6 b5 b4 b3 b2 b1 b0 _________________ ________ ________ ___________________________ ________ 0 c<2:0> counter ls latch selected counter lc latch counter 1 bits: b0 0 read as zero. b1-b3 c<2:0> writing a one in bit 3 causes counter 3 to latch one or both of the registers speicified by lc and ls. the same is true for bits 2 and 1, except that they enable counters 1 and 0 respectively. each counter?s latches remain latched until either the latch is read or the counter is reprogrammed. if ls = lc = 0, status is returned on the next read from the counter. the next one or two reads (depending on whether the counter is programmed to transfer one or two bytes) from the counter result in the count being returned. figure 6-8. read-back command format real time clock and internal timer registers programming the counter timer controller n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-13
b4 ls writing a zero in bit 4 causes the selected counter(s) to latch the current condition of its control register, null count, and output into the status register. the next read of the counter results in the contents of the status register being read. b5 lc writing a zero in bit 5 causes the selected counter(s) to latch to the state of the ce in col and coh. b6-b7 1 read as ones. status byte the format of the status byte command is shown in figure 6-9. b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ _________________ ___________________________ ________ bcd binary coded decimal m<2:0> mode counter f<0:1> flag command nc null count flag out out signal bits: b0 bcd bit 0 indicates the ce is in operation in bcd format. b2-b3 m<0:2> these three bits reflect the mode of the counter and are interpreted in the same manner as in write command operations. b4-b5 f<0:1> bits 4-5 contain the f0 and f1 command bits, which were written to the command register of the counter during initialization. this information is useful when determining whether the high byte, low byte, or both must be transferred during counter read/write operations. b6 nc bit 6 contains the condition of the null count flag. this flag is used to indicate the contents of the ce are valid. nc is set to a one during a write to the control register or the counter. nc is cleared to a zero whevever the counter is loaded from the counter input registers. b7 out bit 7 contains the state of the out signal of the counter. figure 6-9. status byte command n programming the counter timer controller real time clock and internal timer registers 6-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
counter operation due to the previously stated restrictions in counter 0 and counter 1, counter 2 is used as the example in describing counter operation, but the description of modes, 0, 2, 3, and 4 are relevant to all counters. the following terms are defined for describing ctc operation. tmrclk pulse ---- a clock equivalent to osc1 (14.31818 mhz) divided by 12. trigger ---- the rising edge of the gate2 input. counter load ---- the transfer of the 16-bit value in cil and cih to the ce. initialized ---- control word written and the counter input latches loaded. counter 2 operates in one of the following modes: mode 0 ---- interrupt on terminal count writing the control word causes out2 to go low and remain low until the ce reaches zero; at which time it returns to high and remains high until a new count or control word is written. counting is enabled when gate2 = 1. disabling the count has no effect on out2. the ce is loaded with the first tmrclk pulse after the control word and initial count are loaded. when both cil and cih are written, the ce is loaded after cih is written. this tmrclk pulse does not decrement the count (for an initial count of n, out2 does not go high until n+1 tmrclk pulses after initialization). if an initial count is written with gate2 = 0, it is still loaded on the next tmrclk pulse but counting does not begin until gate2 = 1. therefore, out2 goes high n tmrclk pulses after gate2 = 1. mode 1 ---- hardware retriggerable one-shot writing the control word causes out2 to go high initially. once initialized, the counter is armed and a trigger causes out2 to go low on the next tmrclk pulse. out2 then remains low until the counter reaches zero. an initial count of n results in a one-shot pulse n tmrclk cycles long. any subsequent triggers while out2 is low causes the ce to be reloaded, extending the length of the pulse. writing a new count to cil and cih does not affect the current one-shot unless the counter is retriggered. mode 2 ---- rate generator mode 2 functions as a divide-by-n counter, with out2 as the carry. writing the control word during initialization sets out2 high. when the initial count is decremented to one, out2 goes low on the next tmrclk pulse. the following tmrclk pulse returns out2 high, reloads the ce, and the real time clock and internal timer registers counter operation n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-15
process is repeated. in mode 2, the counter continues counting (if gate2 = 1) and generates an out2 pulse every n tmrclk cycles. note that a count of one is illegal in mode 2. gate2 = 0 disables counting and immediately forces out2 high. a trigger releads the ce on the tmrclk pulse. thus gate2 can be used to synchronize the counter to external events. writing a new count while counting does not affect current operation unless a trigger is received. otherwise, the new count is loaded at the end of the current counting cycle. mode 3 ---- square wave generator mode 3 is similar to mode 2 in every respect except for the duty cycle of out2. out2 is set high initially, and remains high for the first half of the count. when the first half of the initial count expires, out2 goes low for the remainder of the count. if the counter is loaded with an even count, the duty cycle of out2 is 50% (high = low = n/2). for odd count values, out2 is high one tmrclk cycle longer than it is low. therefore, high = (n + 1)/2 and low = (n - 1)/2. mode 4 ---- software triggered strobe writing the control word causes out2 to go initially. expiration of the initial count causes out2 to go low for one tmrclk cycle. gate2 = 0 disables counting but has no effect on out2. also, a trigger does not reload the ce. the counting sequence is started by writing the initial count. the ce is loaded on the tmrclk pulse after initialization. the ce begins decrementing one tmrclk pulse later. out2 goes low for one tmrclk cycle, (n + 1) cycles after the initial count is written. if a new initial count is written during a counting sequence, it is loaded into the ce on the next tmrclk pulse and the sequence continues from the new count. this allows the sequence to be retriggered by software. mode 5 ---- hardware triggered strobe writing the control word causes out2 to go high initially. counting is started by a trigger. the expiration of the initial count causes out2 to go low for one tmrclk cycle. gate2 = 0 disables counting. the ce is loaded during counting, the current counting sequence is not affected unless a trigger occurs. a trigger causes the counter to be reloaded from cil and cih making the counter re-triggerable. n counter operation real time clock and internal timer registers 6-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
gate2 in modes 0, 2, 3, and 4 gate2 is level sensitive and is sampled on the rising edge of tmrclk. in modes 1, 2, 3, and 5 the gate2 input is rising-edge sensitive. this rising edge sets an internal flip-flop whose output is sampled on the next rising edge of tmrclk. the flip-flop resets immediately after being sampled. note that in modes 2 and 3 the gate2 input is both edge- and level-sensitive as shown in table 6-4. table 6-4. gate pin function conditions mode low rising high 0 disables counting ---- enables counting 1 ---- a) initiates counting b) resets out pin ---- 2 a) disables counting b) forces high output pin initiates counting enables counting 3 a) disables counting b) forces high output pin initiates counting enables counting 4 disables counting ---- enables counting 5 ---- initiates counting ---- real time clock and internal timer registers counter operation n chips and technologies, inc. p r e l i m i n a r y revision 3.0 6-17
section 7 interrupt controller the 82c836 incorporates two programmable interrupt controllers compatible with the intel 8259a. the controllers accept requests from peripherals, resolve priority on pending interrupts and interrupts in service, issue an interrupt request to the cpu, and provide a vector used as an index by the cpu to determine which interrupt service routine to execute. a variety of priority assignment modes are provided, which can be reconfigured at any time during system operation; allowing the complete interrupt subsystem to be restructured, based on the system requirements. the controllers are cascaded in a fashion compatible with the ibm pc/at. table 7-1 shows the interrupt levels used by the system board and i/o channel. the interrupts are shown by priority, starting with the highest level. table 7-1. interrupt levels for system board interrupt system board i/o channel nmi parity check iochck irq0 timer not available irq1 keyboard not available irq8* real time clock not avaiable irq9 not used available irq10 not used available irq11 not used available irq12 not used available irq13 coprocessor not available irq14 not used available irq15 not used available irq3 serial port 2 available irq4 serial port 1 available irq5 parallel port 2 available irq6 hard disk and floppy disk available irq7 parellel port 1 available * in internal rtc mode, irq8 is an internal signal. chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-1
the two devices are interconnected and must be programmed to operate in cascade mode (see figure 7-1) for proper operation of all 16 interrupt channels. intc1 is located at addresses 020h-021h and is configured for master operation in cascade mode. intc2 is a slave device and is located at 0a0h-0a1h. the interrupt request output signal from intc2 (int) is internally connected to the interrupt request input channel 2 (ir2) of intc1. the address decoding and cascade interconnection matches that of the ibm pc/at. two additional interconnections are made to the interrupt request inputs of the interrupt controllers. the output of timer 0 in the counter/timer subsystem is connected to channel 0 (ir0) of intc1. an interrupt request from the real time clock is connected to channel 0 (ir0) of intc2. the following description of the interrupt subsystem pertains to both intc1 and intc2 unless otherwise noted. whenever register addresses are used, the address for the intc1 register is listed first, and the address for the intc2 register follows in parentheses, e.g., 020h (0a0h). interrupt controller figure 7-1. cascaded interrupt controllers n interrupt controller 7-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
controller operation figure 7-2 shows a block diagram of the major elements in the interrupt controller. the interrupt request register (irr) is used to store requests from all the channels requesting service. interrupt request register bits are labeled using the channel name ir<0:7>. the in-service register (isr) contains all the channels currently being serviced (more than one channel can be in service at the same time). in-service register bits are labeled is<0:7>. the interrupt mask register (imr) allows the cpu to disable any or all of the interrupt channels. the priority resolver evaluates inputs from the above three registers, issues an interrupt request, and latches the corresponding bit into the in-service register. during interrupt acknowledge cycles, a master controller outputs a code to the slave device that is compared in the cascade buffer/comparator with a three bit id code previously written. if a match occurs in the slave controller, it generates an interrupt vector. the contents of the vector register are used to provide the cpu with an interrupt vector during interrupt acknowledge (inta) cycles. figure 7-2. interrupt controller block diagram interrupt controller controller operation n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-3
interrupt sequence the 82c836 allows the cpu to perform an indirect jump to a service routine in response to a request for service from a peripheral device. the indirect jump is based on a vector provided by the 82c836 on the second of two cpu generated inta cycles (the first inta cycle is used for resolving priority; the second cycle is used for transferring the vector to the cpu). the events occurring during an interrupt sequence are as follows: 1. one or more of the interrupt requests (ir7-ir0) becomes active, setting the corresponding irr bit(s). 2. the interrupt controller resolves priority based on the state of irr, imr, and isr and asserts the intr output if appropriate. 3. the cpu accepts the interrupt and responds with an inta cycle. 4. during the first inta cycle, the highest priority isr bit is set and the corresponding irr bit is reset. the internal cascade address is generated and ld<0:7> outputs remain tri-stated. 5. the cpu executes a second inta cycle, during which the 82c836 drives an 8-bit vector onto the data pins ld<0:7>, which is in turn latched by the cpu. the format of this vector is shown in table 7-2. note that v<3:7> is programmable by writing to initialization control word 2. 6. at the end of the second inta cycle, the isr bit is cleared if the automatic end-of-interrupt (aeoi) mode is selected. otherwise, the irs bit must be cleared by an end-of-interrupt (eoi) command from the cpu at the end of the interrupt service routine. table 7-2. interrupt vector format bits vectors ir7 v7 v6 v5 v4 v3 1 1 1 ir6 v7 v6 v5 v4 v3 1 1 0 ir5 v7 v6 v5 v4 v3 1 0 1 ir4 v7 v6 v5 v4 v3 1 0 0 ir3 v7 v6 v5 v4 v3 0 1 1 ir2 v7 v6 v5 v4 v3 0 1 0 ir1 v7 v6 v5 v4 v3 0 0 1 ir0 v7 v6 v5 v4 v3 0 0 0 if no interrupt request is present at the beginning of the first inta cycle (i.e., a spurious interrupt), intc1 issues an interrupt level 7 vector during the second inta cycle. n interrupt sequence interrupt controller 7-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
end-of-interrupt end-of-interrupt (eoi) is defined as the condition causing an isr bit to be reset. determination of which isr bit is to be reset can be done by a cpu command (specific eoi) or the priority resolver can be instructed to clear the highest priority ist bit (nonspecific eoi). the 82c836 can determine the correct isr bit to reset when operated in modes that don?t alter the fully nested structure, since the current highest priority isr bit is necessarily the last level acknowledged and serviced. in conditions where the fully nested structure is not preserved, a specific eoi must be generated at the end of the interrupt service routine. an isr bit that is masked, in special mask mode by an imr bit, is not cleared by a nonspecific eoi command. optionally, the interrupt controller can generate an automatic end-of-interrupt (aeoi) on the trailing edge of the second inta cycle. controller ready end of initialization xa0 = 1 write icw4 icw4? xa0 = 1 write icw3 yes yes no no mode cascade xa0 = 1 xa0 = 0 xd4 = 1 write icw2 write icw1 start figure 7-3. initialization sequence interrupt controller end-of-interrupt n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-5
priority assignment assignment of priority is based on an interrupt channel?s position relative to the other channels in the interrupt controller. after the initialization sequence, ir0 has the highest priority, ir7 has the lowest, and priority assignment is fixed (fixed priority mode). priority assignment can be rotated either manually (specific rotation mode) or automatically (automatic rotation mode) by programming operational command word 2 (ocw2). fixed priority mode this is the default condition that exists unless rotation (either manual or automatic) is enabled, or the controller is programmed for polled mode. in fixed priority mode, interrupts are fully nested with priority assigned as shown in the following figure. figure 7-4. fixed priority mode lowest highest priority status b7 b6 b5 b4 b3 b2 b1 b0 nesting allows interrupts with higher priorities to generate interrupt requests prior to the completion of the interrupt in service. when an interrupt is acknowledged, priority is resolved, the highest priority request?s vector is placed on the bus, and the isr bit for that channel is set. this bit remains set until an eoi (automatic or cpu generated) is issued to that channel. while the isr bit is set, all interrupts of equal or lower priority are inhibited. note that a higher priority interrupt that occurs during an interrupt service routine, is acknowledged only if the cpu has internally re-enabled interrupts. n end-of-interrupt interrupt controller 7-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
specific rotation mode specific rotation allows the system software to reassign priority levels by issuing a command that redefines the highest priority channel. figure 7-5 illustrates the result of a specific rotation command, assigning highest priority to channel 5. lowest highest priority status 7 6 5 4 3 2 1 0 before rotation priority status 5 4 3 2 1 0 7 6 after rotation automatic rotation mode in applications in which a number of equal priority peripherals are requesting interrupts, automatic rotation may be used to equalize the priority assignment. in this mode, a peripheral, after being serviced, is assigned the lowest priority. all peripherals connected to the controller are serviced at least once in eight interrupt requests to the cpu from the controller. automatic rotation occurs, if enabled, due to the occurrence of eoi (automatic or cpu generated). is7 is6 is5 is4 is3 is2 is1 is0 isr status bit 0 1 0 1 0 before rotation priority status 7 6 5 4 3 2 1 0 lowest highest is7 is6 is5 is4 is3 is2 is1 is0 isr status bit 0 1 0 after rotation priority status 4 3 2 1 0 7 6 5 lowest highest figure 7-5. specific rotation mode figure 7-6. automatic rotation mode interrupt controller end-of-interrupt n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-7
programming the interrupt controller two types of commands are used to control the 82c836 interrupt controllers: initialization command words (icws) and operational command words (ocws). initialization command words the initialization process consists of writing a sequence of four bytes to each interrupt controller. the initialization sequence is started by writing the first initialization command word (icw1) to address 020h (0a0h) with a one on bit 4 of the data byte. the interrupt controller interprets this as the start of the initialization sequence and does the following: 1. the initialization command word counter is reset to zero. 2. icw1 is latched into the device. 3. fixed priority mode is selected. 4. ir7 is assigned the highest priority. 5. the interrupt mask register is cleared. 6. the slave mode address is set to seven. 7. special mask mode is disabled. 8. the irr is selected for status read operations. the next three i/os write to address 021h (0a1h) will load icw2-icw4. see figure 7-3 shown earlier for a flow chart of the initialization sequence. the initialization sequence can be terminated at any point (all four bytes must be written for the controller to be properly initialized) by writing to address 020h (0a0h) with a zero in data bit 4. note that this causes ocw2 or ocw3 to be written. n programming the interrupt controller interrupt controller 7-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
b7 b6 b5 b4 b3 b2 b1 b0 ___________________________ ________ ________ ________ ________ ________ x sm single mode x ltm level triggered mode si sequence initialization x bits: b0 x this bit is ignored. b1 sm bit 1 selects between single mode and cascade mode. single mode is used whenever only one interrupt controller (intc1) is used and is not recommended for this device. cascade mode allows the two interrupt controllers to be connected through ir2 of intc1. intc1 allows intc2 to generate its own interrupt vectors if cascade mode is selected and the higest priority ir pending is from an intc2 input. intc1 and intc2 must be programmed for cascade mode for both devices to operate. b2 x this bit is ignored. b3 ltm bit 3 selects the level or edge triggered inputs to the irr. if a one is written to ltm, a high-level on the irr input generates an interrupt request. the ir must be active until the first inta cycle is started to generate the proper interrupt vector (an ir7 vector is generated if the irr input is de-asserted early), and the ir must be removed prior to eoi to prevent a second interrupt from occuring. b4 si bit 4 indicates to the interrupt controller that an initialization sequence is starting and must be a one to write icw1. b5-b7 x these bits are ignored. figure 7-7. icw1 ---- address 020h (0a0h) write only interrupt controller programming the interrupt controller n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-9
b7 b6 b5 b4 b3 b2 b1 b0 ______________________________________________ ___________________________ x v<7:3> interrupt vector bits: b0-b2 x these bits are ignored. b3-b7 v<7:3> these bits are the upper five bits of the interrupt vector and are programmable by the cpu. the lower three bits of the vector are generated by the priorty resolver during inta. intc1 and intc2 need not be programmed with the same value in icw2. b7 b6 b5 b4 b3 b2 b1 b0 __________________________________________________________________________ s<7:0> slave mode bits: b0-b7 s<7:0> select which ir inputs have slave mode controllers connected. icw3 in intc1 must be written with 04h for intc2 to function. b7 b6 b5 b4 b3 b2 b1 b0 ______________________________________________ ___________________________ id<2:0> identify slave mode address 0 bits: b0-b2 id<2:0> determine the slave mode address the controllers will respond to during the cascaded inta sequence. icw3 in intc2 should be written with 02h for cascade mode operation. note that b3-b7 should be zero. b3-b7 0 these bits are zeros. figure 7-8. icw2 ---- address 021h (0a1h) write only figure 7-9. icw3 format for intc1 ---- address 021h write only figure 7-10. icw3 format for intc2 ---- address 0a1h write only n programming the interrupt controller interrupt controller 7-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
b7 b6 b5 b4 b3 b2 b1 b0 ___________________________ ________ _________________ ________ ________ x aeoi auto end-of-interrupt x emi enable multiple interrupts x bits: b0 x this bit does not matter. b1 aeoi auto end-of-interrupt is enabled when icw4 is written with a zero in both interrupts. the interrupt controller performs a non-specific eoi on the trailing edge of the second inta cycle. note that this function should not be used in a device with fully nested interrupts, unless the device is a cascade master. b2-b3 x these bits are ignored. b4 emi bit 4 enables multiple interrupts from the same channel in fixed priority mode. this allows intc2 to fully nest interrupts when cascade mode, with fixed priority mode, are both selected without being blocked by intc1. correct handling of this mode requires the cpu to issue a nonspecific eoi command to intc2 and check its in-service register for zero when exiting an interrupt service routine. if zero, a nonspecific eoi command should be sent to intc1. if nonzero, no command is issued. b5-b7 x these bits are ignored. figure 7-11. icw4 ---- address 021h (0a1h) write only interrupt controller programming the interrupt controller n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-11
operational command words operational command word one (ocw1) is located at address 021h (0a1h) and may be written any time the controller is in initialization mode. operational command words two and three (ocw2 and ocw3) are located at address 020h (0a0h). writing to address 020h (0a0h) with a zero in bit 4 places the controller in oeprational mode and loads ocw2 (if data bit 3 = 0) or ocw3 (if data bit 3 = 1). b7 b6 b5 b4 b3 b2 b1 b0 __________________________________________________________________________ m<7:0> master register interrupt bits: b0-b7 m<7:0> these bits control the state of the interrupt mask register. each interrupt request can be masked by writing a one in the appropriate bit position (m0 controls ir0 etc.) setting an imr bit has no effect on lower priority requests. all imr bits are cleared by writing icw1. figure 7-12. ocw ---- address 021h (0a1h) read/write n programming the interrupt controller interrupt controller 7-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ ________ ________ ________ __________________________ l<2:0> interrupt channel select 0 si select initialization mode eoi enable operational interrupt sl select operational function r rotation function select bits: b0-b3 l<2:0> these three bits are internally decoded to select which interrupt channel is to be affected by the specific command. l<2:0> must be valid during three of the four specific cycles (see sl). b3 0 this bit is zero. b4 si writing a zero in this bit position takes the interrupt controller out of initialize mode and writes ocw2 or ocw3. b5 eoi this bit, in conjunction with r and sl, selects operational function. writing a one in this bit position causes a function related to eoi to occur. nonspecific eoi command when r = 0 and sl = 1 and eoi = 0 specific eoi command when r = 0 and sl = 1 and eoi = 1 rotate on nonspecific eoi when r = 1 and sl = 0 and eoi = 1 rotate on specific eoi when r = 1 and sl = 1 and eoi = 1 b6 sl this bit, in conjunction with r and eoi, selects operational function. writing a one in this bit position causes a specific or immediate function to occur. all specific commands require l<2:0> to be valid, except no operation. no operation when r = 0 and sl = 1 and eoi = 0. specific eoi command when r = 0 and sl = 1 and eoi = 1. specific rotate command when r = 1 and sl = 1 and eoi = 0. rotate on specific eoi when r = 1 and sl = 1 and eoi = 1. b7 r this bit together with sl and eoi selects operational function. writing a one in bit 7 causes one of the rotate functions to be selected. rotate on auto eoi enable. (note: this function is disabled by writing a zero to all three bit positions.) when r = 1 and sl = 0 and eoi = 0. rotate on nonspecific eoi when r = 1 and sl = 0 and eoi = 1. specific roate command when r = 1 and sl = 1 and eoi = 0. rotate on specific eoi when r = 1 and sl = 1 and eoi = 1. figure 7-13. ocw2 ---- address 020h (0a0h) write only interrupt controller programming the interrupt controller n chips and technologies, inc. p r e l i m i n a r y revision 3.0 7-13
b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ ________ ________ ________ ________ ________ ________ ris select between irr and isr rr read register pm polled mode 1 si select initialization mode smm special mask mode esmm enable set/reset special mask mode 0 bits: b0 ris this bit selects between the irr and the isr during status read operations if rr = 1. irr is selected if this bit is set to one. isr is selected if this bit is set to zero. b1 rr when the rr bit is one, reading the status port at address 020h (0a0h) causes the contents of irr or isr (determined by ris) to be placed on xd<7:0>. asserting pm forces rr reset. b2 pm polled mode is enabled by writing a one to bit 2 of ocw3 causing the 82c836 to perform the equivalent of an inta cycle during the next i/o read operation to the controller. the byte read during this cycle sets bit 7 if an interrupt is pending. if bit 7 of the byte is set, the level of the highest pending request is encoded on bit 2-0. the irr remains frozen until the read cycle is completed, at which time the pm bit is reset. b3 1 this bit is set to one. b4 si see si shown in ocw2. b5 smm if esmm and smm are both written with a one, the special mask mode is enabled. writing a one to esmm and a zero to smm disables special mask mode. during special mask mode, writing a one to any bit position inhibits interrupts; a zero enables interrupts on the associated channel by causing the priority resolver to ignore the condition for the isr. b6 esmm writing a one in this bit position enables the set/reset special mask mode function controlled by bit 5 (smm). esmm allows the other functions in ocw3 to be accessed and manipulated without affecting the special mask mode state. b7 0 this bit is set to zero. figure 7-14. ocw3 ---- address 020h (0a0h) write only n programming the interrupt controller interrupt controller 7-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 8 dma controller memory refresh and dma functions are implemented within the 82c836 as independent bus masters, i.e., the refresh controller is separate from the 8237-compatible dma controllers. the 82c836 arbitrates refresh and dma functions with internal logic and gains control of the local bus via the hold/hlda protocol of the 80386sx. the 82c836 contains two dma controllers compatible with the intel 8237. each controller is a four-channel dma device that can generate the memory addresses and control signals necessary to transfer information directly between a peripheral device and memory. this allows efficient information transfer with little cpu intervention and a minimum of bus overhead. the two dma controllers are internally cascaded to provide four dma channels for transfers to 8-bit peripherals (dma1), and three channels for transfers to 16-bit peripherals (dma2). dma2, channel 0, provides the cascade interconnetion for the two dma devices, thereby maintaining ibm pc/at compatibility. figure 8-1 shows how the two controllers are cascaded. dma channels 0-3 are used for 8-bit transfers, while channels 5-7 are used for 16-bit transfers. dma operations are allowed within the full range of 16mb memory through the use of dma page registers. figure 8-1. cascaded dma controllers chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-1
the dma clock, internal to the 82c836, controls the dma transfer rate and timing. it is derived from the busclk and is selectable as either busclk/2 (default, at-compatible) or busclk. wait states during dma operations are programmed with internal configuration register 01h, bits 5-2. refresh, which occurs at 15 m s intervals (nominally), is determined by counting down the 1.19mhz (osc1/12) clock. the refresh period is set by programming timer channel 1 of the 8254 timer/counter. table 8-1 shows the usage of dma levels on the i/o channel. the dma requests are shown by priority, starting with the highest level. table 8-1. dma request levels for each i/o channel dma level system board i/o channel drq0 not used available drq1 not used available drq2 not used diskette drive drq3 not used available drq4 not used available drq5 not used available drq6 not used available drq7 not used available dma cycle length control is provided internally in the 82c836 allowing independent control for both 8-bit and 16-bit cycles. this is done through the programmable registers, which can extend command signals or insert wait states. each dma channel has a pair of 16-bit counters and a reload register for each counter. the 16-bit counters allow the dma to transfer blocks as large as 65,536 words. the register, associated with each counter, allows the channel to reinitialize without programming. the following description of the dma subsystem pertains to both dma1 and dma2 unless otherwise noted. although the 8237 provides a ?? memory-to-memory ?? mode of transfer, this 8237- compatible mode is not usable in pc at-compatible architectures, including scatsx. the memory-to-memory mode requires the use of the temporary data holding register in the 8237, which is not accessible during dma because of the way the bus buffers are controlled. furthermore, at-compatible architectures, such as scatsx, do not contain steering logic to allow memory write data to come from the 8237 instead of an i/o resource. it is possible that 8-bit memory-to-memory transfers might work successfully anyway (accidentally) if there is sufficient bus capacitance to preserve the data between the memory read cycle and memory write cycle, but this approach cannot be considered reliable. information concerning memory-to-memory transfer is included in this datasheet only because the 82c836 implements the same 8237-compatible functionality found in the pc/at. dma controller n dma controller 8-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
dma operations during normal operation of the 82c836, the dma subsystem is in either an idle condition, a program condition, or an active condition. in idle condition, the dma controller executes cycles consisting of only one state. the idle state, si, is the default condition, and the dma remains in this condition unless the device has been initialized and one of the dma requests is active, or the cpu attempts to access one of the internal registers. when a dma request becomes active, the device enters the active condition and issues a hold request to the system. once in the active condition, the 82c836 generates the necessary memory addresses and command signals to accomplish a memory-to-i/o or i/o-to-memory transfer. timing for memory-to-memory transfer can also be generated (but without access to the data holding register). memory-to-i/o and i/o-to-memory transfers take place in one bus cycle, while memory-to-memory transfer timing requires two bus cycles. during transfers between memory and i/o, data is presented on the system bus by either memory or the requesting device, and the transfer is completed in one bus cycle. memory-to-memory transfers, however, require that the dma store data from the read operation in an internal register, which is not accessible in at-compatible architectures. during transfers between memory and i/o, two commands are activated during the same bus cycle. in the case of a memory-to-i/o transfer, the 82c836 asserts both -xmemr and -iow, allowing data to be transferred directly to the requesting device from memory. note, the 82c836 neither latches data from, or drives data out on this type of cycle. the number of clock cycles required to transfer a word of data may be varied by programming the dma, or may be optionally extended by the peripheral device. during an active cycle, the dma goes through a series of states. each state is one dma clock cycle in length, and the number of states in a cycle varies depending on how the device is programmed and the type of cycle being performed. the states are labeled s0-s4. idle condition when no device is requesting service, the dma is in an idle condition keeping the state machine in the si state. during this time, the 82c836 samples the dreq input pins every clock cycle. the internal select from the top level decoder and hlda are also sampled at the same time to determine if the cpu is attempting to access the internal registers. when either of these situations occurs, the dma exits the idle condition. note, the program condition has priority over the active condition since a cpu cycle has already started. dma controller dma operations n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-3
program condition the program condition is entered whenever hlda is inactive and internal select is active. the internal select is derived from the top-level decode (described earlier). during this time, address lines a0-a3 become inputs if dma1 is selected, or a1-a4 become inputs if dma2 is selected. note: when dma2 is selected, a0 is ignored. these address inputs are used to select the dma controller registers to be read or written. due to the large number of internal registers in the dma subsystem, an internal flip-flop is used to supplement the addressing of the count and address registers. this bit is used to select between the high and low bytes of these registers. the flip-flop toggles each time a read or write occurs to any of the word count or address registers in the dma. the internal flip-flop is cleared by a hardware reset or a master clear command and may be set or cleared by the cpu issuing the appropriate command. special commands are supported by the dma subsystem in the program condition to control the device. these commands do not make use of the data bus, but are derived from a set of addresses, the internal select, and -iow or -ior. these commands are master clear, clear register, clear mode register counter, set, and clear byte pointer flip-flop. the 82c836 enables programming whenever hlda has been inactive for one dma clock cycle. it is the responsibility of the system to ensure that programming and hlda are mutually exclusive. erratic operation of the 82c836 can occur if a request for service occurs on an unmasked channel that is being programmed. the channel should be masked, or the dma disabled, to prevent the 82c836 from attempting to service a device with a channel which is partially programmed. active condition the 82c836 dma subsystem enters the active condition whenever a software request occurs or a dma request on an unmasked channel occurs, and the device is not in the program condition. the 82c836 then begins a dma transfer cycle. in an i/o-to-memory cycle, for example, after receiving a dreq, the 82c836 asserts hold to the cpu. on the next clock cycle, the dma exits the idle condition and enters state s0, where it remains until hlda is returned. after detecting hlda, the dma enters state s1, during which the dma controller generates the memory address, resolves priority and issues dack on the highest priority channel requesting service. the dma then proceeds to state s2, at which time the 82c836 asserts -xior. next, the device transitions into s3, where the -xmemw command is asserted. this is followed by a minimum of one dma wait state, sw, where the 82c836 remains until the wait-state counter has decremented to zero and iochrdy is true. at least one sw always occurs, but the s3 state can be deleted if the compressed timing is selected. once a ready condition is detected, the dma enters s4, where both commands are deasserted. in n dma operations dma controller 8-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
burst mode and demand mode, subsequent cycles begin in s2, unless the intermediate address bits require updating. in these subsequent cycles, the lower address bits are changed in s2. the dma can be programmed on a channel-by-channel basis to operate in one of four modes. the four mode are described as follows: single transfer mode ---- this mode directs the dma to execute only one transfer cycle at a time. dreq must be held active until dack becomes active. if dreq is held active throughout the cycle, the 82c836 deasserts hrq and releases the bus after the transfer is complete. after hlda is inactive, the 82c836 again asserts hrq and executes another cycle in the same cycle; unless a request from a higher priority channel is received. in this mode, the cpu is allowed to execute at least one bus cycle between transfers. following each transfer, the word count is decremented and the address is incremented or decremented. when the word count decrements from 0000h to ffffh, the terminal count bit in the status register is set and a t/c pulse is generated. if auto-initialization option is enabled, the channel reinitialized itself. if auto-initialize is not selected, the dma sets the dma request bit mask and suspends transferring on the channel. block transfer mode ---- when block transfer mode is selected, the 82c836 begins transfers in response to either a dreq or a software request. this continues until a terminal count (ffffh) is reached, at which time tc is pulsed and the status register terminal count bit is set. in this mode dreq need only be held active until dack is asserted. auto-initialization is operational in this mode also. demand tranfer mode ---- in demand transfer mode, the dma begins transfers in response to the assertion of dreq and continues until either terminal count is reached or dreq becomes inactive. this mode is normally used for peripherals with limited buffering availability. the perpheral can initiate a transfer and continue until its buffer capacity is exhausted. the peripheral may re-establish service by again asserting dreq. during idle periods, between transfers, the cpu is released to operate and can monitor the operation by reading intermediate values from the address and word count register. once dreq is deasserted, higher priority channels are allowed to intervene. reaching terminal count results in the generation of a tc pulse, the setting of the terminal count bit in the status register, and auto-initialization (if enabled). cascade mode ---- this mode is used to interconnect more than one dma controller, to extend the number of dma channels while preserving the priority chain. in cascade mode, the master dma controller does not generate address or control signals. the dreq and dack signals of the master are used to interface the hrq and hlda signals of the slave dma devices. once the master has received an hlda from the cpu in response to a dreq caused by the hrq from a slave dma controller, the master dma controller ignores all inputs except hlda from the cpu and dreq on the active channel. this prevents conflicts between the dma devices. figure 8-1 (shown earlier), portrays the cascade interconnection between the two levels of dma devices. note, channel 0 of dma2 is internally connected for cascade mode to dma1. additional devices can be cascaded to the available channels in either dma1 or dma2 since cascade is not limited to two levels for dma controllers. dma controller dma operations n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-5
when programming cascaded controller, begin with the device which is actually generating hrq to the system (first level device) and then proceed to the second level device. reset causes the dack outputs to become active low and are placed into an inactive state. to allow the internal cascade between dma1 and dma2 to function correctly, the active low state of dack should not be modified. this is because the 82c836 has an inverter between dack0 of dma2 and hlda of dma1. this first level device?s dma request mask bit prevents second level cascaded devices from generating unwanted hold requests during the initialization process. dma transfers four types of transfer modes are provided in the 82c836 dma subsystem. these transfer types are: read transfer ---- read transfers move data from memory to an i/o device by generating the memory address and asserting -xmemr-and -xiow during the same cycle. write transfer ---- write transfers move data from an i/o device to memory by generating the memory address and aserting -xior and -xmemw. memory-to-memory transfer ---- (not usable in at-compatible architectures.) the memory-to-memory transfer in an 8237 is designed to move a block of data from one location in memory to another. dma channels 0 and 1 may be programmed to operate as memory-to-memory channels by setting a bit in the command register. once programmed to perform a memory-to-memory transfer, the process can be started by generating either a software request or an external request to channel 0. once the transfer is initiated, channel 0 provides the address for the source block during the memory read portion of the cycle. channel 1 generates the address for the memory write cycle. during the read cycle, the 8237-compatible subsection attempts to latch a byte of data in the internal temporary register (not accessible in at-compatible architectures). the 8237-compatible subsection then attempt to output the contents of the temporary register on the xd0-7 data lines during the write portion of the cycle, so the data can subsequently be written to memory. however, at-compatible architectures, including scatsx, do not contain the necessary data bus steering logic to implement this data path. channel 0 may be programmed to maintain the same source address on every cycle, so the cpu can initialize blocks of memory with the same value. the 82c836 continues to perform transfer cycles until channel 1 reaches terminal count. verify transfer ---- the verify transfer is a pseudo-transfer useful for diagnostics. in this type of transfer, the dma operates as if it is performing a read or write transfer by generating hrq, address, and dack, but does so without asserting a command signal. since no transfer actually takes place, iochrdy is ignored during verify transfer cycles. auto-initialization each of the four dma channel mode registers contain a bit that causes the channel to reinitialize after reaching terminal count. during this process, referred to as auto-initialization, the base address and base word count registers, which were n dma transfers dma controller 8-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
originally written by the cpu, are reloaded into the current address and current word count registers (both the base and current registers are loaded during a cpu write cycle). the base register remains unchanged during dma active cycles and can only be changed by the cpu. if the channel is programmed to auto-initialize, the request mask bit is not set upon reaching terminal count. this allows the dma to continue operation without cpu intervention. during memory-to-memory transfers, the word count registers of both channel 0 and channel 1 must be programmed with the same starting value for full auto-initialization. if channel 0 reaches terminal count before channel 1, then channel 0 and channel 1 must be programmed with the same starting value for full auto-initialization. if channel 0 reaches terminal count before channel 1, then channel 0 reloads the starting address and word count, and continues transferring data from the beginning of the source block. should channel 1 reach terminal count first, it reloads the current registers and channel 0 remains uninitialized. dreq priority the 82c836 supports two schemes for establishing dreq priority. the first is fixed priority, which assigns priority based on channel position. in this method, channel 0 is assigned the highest priority. priority assignment then progresses in order down through channels, with channel 3 receiving the lowest priority. the second type of priority assignment is rotating priority. in this scheme the ordering of priority from channel 0 to channel 3 is maintained but the actual assignment of priority changes. the channel most recently serviced is assigned the lowest priority and, since the order of priority assignment remains fixed, the remaining three channels rotate accordingly. in instances where multiple requests occur at the same time, the 82c836 issues an hrq but does not freeze the priority logic until hlda is returned. once hlda becomes active, the priority logic is frozen and dack is asserted on the highest requesting channel. priority is not re-evaluated until hlda is deactivated. address generation dma addresses consist of three separate parts: the low-order bits (0-7 or 1-8) are automatically incremented after each dma transfer (during state s1 or s2). the middle bits (8-15 or 9-16) are updated only when there is a carry from the low order bits. an s1 state is required whenever the middle bits need to be updated. the high-order bits (16-23 or 17-23) come from the dma page registers, separate from the 8237-compatible dma subsections. the high-order bits cannot be updated without software intervention. dma controller dma transfers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-7
during demand and block transfers, the 82c836 generates multiple sequential transfers. for most of these transfers only the low-order address bits need to change. the 82c836 updates the middle bits only when necessary. this results in an overall throughput improvement, since s1 states are not necessary when only the low-order bits are updated. the dma page register file is a set of 16 8-bit registers in the 82c836 used to generate the high order address bits during dma cycles. only eight of the registers are actually used, but all sixteen are included to maintain ibm pc/at compatibility. each dma channel has a register associated with it, except for channel 0 of dma2, which is used for internal cascading to dma1. i/o address assignments for these registers are shown in table 8-2. table 8-2. dma page register function i/o ports i/o port register function i/o port register function 080h unused 088h unused 081h 8-bit dma channel 2 (dack2) 089h 16-bit dma channel 2 (dack6) 082h 8-bit dma channel 3 (dack3) 08ah 16-bit dma channel 3 (dack7) 083h 8-bit dma channel 1 (dack1) 08bh 16-bit dma channel 1 (dack5) 084h unused 08ch unused 085h unused 08dh unused 086h unused 08eh unused 087h 8-bit dma channel 0 (dack0) 08fh refresh cycle i/o port 80h is normally used externally for diagnotic leds, and is updated by the at-compatible bios during the power-on self-test (post). the leds are optional; they can either be designed onto the motherboard (usually for evaluation and testing purposes only), or they can be provided on a removable at bus add-on card. compressed timing the dma subsystem in the 82c836 can be programmed to transfer a word in as few as three dma clock cycles (states). the normal at-compatible dma cycle consists of four states: s2, s3, sw, and s4 (this assumes demand or block transfer mode). additional dma wait states (sw) can be programmed. in systems capable of supporting high throughput, the 82c836 can be programmed to omit the s3 state and assert both commands in s2. this reduces the minimum cycle to just s2, sw, and s4. if compressed timing is selected, tc is output in s2, and s1 cycles are executed as necessary to update the middle address bits. compressed timing is not allowed in the memory-to-memory transfer mode. n dma transfers dma controller 8-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
dma register descriptions the following sections describe the registers used during dma functions. current address register each dma channel has a 16-bit current address register that holds the address used during transfers. each channel can be programmed to increment or decrement this register whenever a transfer is completed. this register can be read or written by the cpu in consecutive 8-bit bytes. if auto-initialization is selected, this register is reloaded from the base address register upon reaching terminal count in the current word count register. channel 0 can be prevented from incrementing or decrementing by setting the address hold bit in the command register. current word count register each channel has a current word count register that determines the number of transfers to perform. the actual number of transfers performed is one greater than the value programmed into the register. the register is decremented after each transfer until it goes from zero to ffffh. when this roll-over occurs, the 82c836 generated t/c, suspends operation on that channel, sets the appropriate request mask bit or auto-initialize, and continues. base word count register this register preserves the initial value of the current word count register. it is also a write-only register loaded by writing to the current word count register. this register is loaded in the current word count register during auto-initialization. command register this register controls the overall operation of a dma subsystem. the register can be read or written by the cpu and is cleared by either a reset or a master clear command. see figure 8-2 for the command register format. dma controller dma register descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-9
b7 b6 b5 b4 b3 b2 b1 b0 ________ ________ ________ ________ ________ ________ ________ ________ m-m memory-to-memory transfers ah address hold feature enable cd controller for dma ct compressed timing rp rotating priority scheme ew extended write dreq dack bits: b0 m-m a one in the bit 0 position enables channel 0 and channel 1 to be used for memory-to-memory transfers. b1 ah writing a one to bit 1 enables the address hold feature in channel 0 when performing memory-to-memory transfers. b2 cd bit 2 is the master disable for the dma controller. writing a one to this location disables the dma subsystem (dma1 or dma2). this function is normally used whenever the cpu needs to reprogram one of the channels to prevent dma cycles from occuring. b3 ct compressed timing is enabled by writing a one to bit 3 of this register. the default 0 condition causes the dma to operate with normal timing. b4 rp writing a one to bit 4 causes the 82c836 to utilize a rotating priority scheme for honoring dma requests. the default condition is fixed priority. b5 ew extended write is enabled by writing a one to bit 5, causing the write command to be asserted one dma cycle earlier during a transfer. the read and write commands both begin in state s2 when enabled. b6 dreq dreq active level is determined by bit 6. writing a one in this bit position causes dreq to become active low. b7 dack dack active level is determined by bit 7. programming a one in this bit position makes dack an active high signal. mode register each dma channel has a mode register associated with it. all four mode registers reside at the same i/o address. bits 0 and 1 of the write mode register command determine which channel?s mode register is written to. the remaining six bits control the mode of the selected channel. each channel?s mode register can be read by sequentially figure 8-2. command register n dma register descriptions dma controller 8-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
reading the mode register location. a clear mode register counter command is provided to allow the cpu to restart the mode read process at a known point. during mode read operation, bits 0 and 1 are one. refer to figure 8-3. b7 b6 b5 b4 b3 b2 b1 b0 _________________ ________ ________ _________________ _________________ cs<1:0> channel select tt<1:0> type of transfer ai auto-initialization dec address counter direction m<1:0> mode selection bits: b0-b1 cs<1:0> channel select bits 1 and 0 determine the channel for which the mode register is written. read back of a mode register results in bits 1 and 0 both being ones. channel select is as follows: channel 0 select when cs1 = 0 and cs0 = 0 channel 1 select when cs1 = 0 and cs0 = 1 channel 2 select when cs1 = 1 and cs0 = 0 channel 3 select when cs1 = 1 and cs0 = 1 b2-b3 tt<1:0> bits 2 and 3 control the type of transfer that is to be performed. the type of transfer is as follows: verify transfer when tt1 = 0 and tt0 = 0 write transfer when tt1 = 0 and tt0 = 1 read transfer when tt1 = 1 and tt0 = 0 illegal when tt1 = 1 and tt0 = 1 b4 ai the auto-initialization function is enabled by writing a one in bit 4 of the mode register. b5 dec determines direction of the address counter. a one in bit 5 decrements the address after each transfer. b6-b7 m<1:0> mode selection for each channel is accomplished by bit 6 and 7. the type of modes are as follows: demand mode when m1 = 0 and m0 = 0 single cycle mode when m1 = 0 and m0 = 1 block mode when m1 = 1 and m0 = 0 cascade mode when m1 = 1 and m0 = 1 figure 8-3. mode register dma controller dma register descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-11
request register this is a four-bit register used to generate software requests. (dma service can be requested either externally or under software control). request register bits can be set or reset independently by the cpu. the request mask has no effect on software generated requests. all four bits are read in one operation and appear in the lower four bits of the byte. bits 4 through 7 are read as ones. all four request bits are cleared to zero by a reset. b7 b6 b5 b4 b3 b2 b1 b0 ______________________________________________ ________ _________________ rs<1:0> request channel select rb request bit x bits: b0-b1 rs<1:0> channel select 0 and 1 determine which channel?s mode register is written to. read back for the mode register results in bits 0 and 1 both being ones. channel 0 select when rs1 = 0 and rs0 = 0 channel 1 select when rs1 = 0 and rs0 = 1 channel 2 select when rs1 = 1 and rs0 = 0 channel 3 select when rs1 = 1 and rs0 = 1 b2 rb the request bit is set by writing a one to bit 2. rs1-rs0 select which bit (channel) is to be manipulated. b3-b7 x these bits are ignored. figure 8-4. request register (write operaton) n dma register descriptions dma controller 8-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
the format for the request register read operation is shown in figure 8-5. b7 b6 b5 b4 b3 b2 b1 b0 ____________________________________ ____________________________________ rc<3:0> request channel 1 bits: b0-b3 rc<3:0> during a request register read, the state of the request bit associated with each channel is returned in bits 0 through 3 of the byte. the bit position corresponds to the channel number. b4-b7 1 these bits are read as ones. request mask register the request mask register is a set of four bits that are used to inhibit external dma requests from generating transfers cycles. this register can be programmed in two ways. each channel can be independently masked by writing to the write single mask bit location. the data format for this operation is shown as follows: b7 b6 b5 b4 b3 b2 b1 b0 ______________________________________________ ________ __________________ ms<1:0> select mask mb mask bit x bits: b0-b1 ms<0:1> these two bits select the specific mask bit that is to be set or reset. channel 0 select when ms1 = 0 and ms0 = 0 channel 1 select when ms1 = 0 and ms0 = 1 channel 2 select when ms1 = 1 and ms0 = 0 channel 3 select when ms1 = 1 and ms0 = 1 figure 8-5. request register read format figure 8-6. request mask register ---- write single mask bit dma controller dma register descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-13
b2 mb bit 2 sets or resets the request mask bit for the channel selected by ms1 and ms0. writing a one in this bit position sets the mask, inhibiting external requests. b3-b7 x these bits are ignored. alternatively, all four mask bits can be programmed in one operation by writing to the write all mask bits address. the data format for this function and the read all mask bits function is shown in figure 8-7. b7 b6 b5 b4 b3 b2 b1 b0 ____________________________________ ____________________________________ mb<3:0> mask bit x bits: mb<3:0> each bit position in the field represents the mask bit of a channel. the mask bit number corresponds to the channel number associated with the mask bit. all four mask bits are set following a reset or a master clear command. individual channel mask bits are set as a result of terminal count being reached, if auto-initialize is disabled. the entire register can be cleared, enabling all four channels, be performing a clear mask register operation. b4-b7 these bits are ignored. figure 8-7. request mask register ---- write all mask bits n dma register descriptions dma controller 8-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
status register the status of all four channels can be determined by reading the status register. information is available to determine if a channel has reached terminal count and whether an external service request is pending. bit 0-3 of this register are cleared by a reset, a master clear, or each time a status read takes place. bits 4-7 are cleared by a reset, a master clear, or the pending request bits. the channel number corresponds to the bit position. refer to figure 8-8. b7 b6 b5 b4 b3 b2 b1 b0 ____________________________________ ____________________________________ tc<3:0> terminal count drq<3:0> dma request bits: b0-b3 tc<3:0> terminal count reached. b4-b7 drq<3:0> dma request pending temporary register the temporary register (not accessible in at-compatible architectures, including scatsx) is used as a temporary holding register for data during memory-to-memory transfers. the register is loaded during the first cycle of a memory-to-memory transfer from xd0-7. during the second cycle of the transfer, the 8237-compatible subsection attempts to output the data on the xd0-7 pins, but there is no bus steering logic implementing this data path. data from the last memory-to-memory transfer remains in the register unless a reset or a master clear occurs. figure 8-8. status register (read only) dma controller dma register descriptions n chips and technologies, inc. p r e l i m i n a r y revision 3.0 8-15
special commands five special commands are provided to make the task of programming the device easier. these commands are activated as a result of a specific address and assertion of either an -ior or -iow. information on the data lines is ignored by the 82c836 whenever an -iow activated command is issued. thus data returned on -ior activated commands is invalid. decriptions of the five special commands follows: clear byte pointer flip-flop ---- this command is normally executed prior to reading or writing to the address or word count register. this initializes the flop-flop to point to the low byte of the register and allows the cpu to read or write the register bytes in correct sequence. set byte pointer flip-flop ---- setting the byte pointer flip-flop allows the cpu to adjust the pointer to the high byte of an address or word count register. master clear ---- this command has the same effect as a hardware reset. the command register, status register, request register, temporary register, mode register counter, and byte pointer flip-flop are cleared and the request mask register is set. immediately following master clear or reset, the dma is in the idle condition. clear request mask register ---- this command enables all four dma channels to accept requests by clearing the mask bits in the register. clear mode register counter ---- in order to allow access to four mode registers while only using one address, an additional counter is used. after clearing the counter, all four mode registers may be read by doing successive reads to the read mode register address. the order in which the register is read is channel 0 first and channel 3 last. n dma register descriptions dma controller 8-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 9 address maps i/o address maps the following tables identify the i/o ports used in the 82c836. for information regarding reserved locations, consult the ibm pc/at technical reference manual. table 9-1. dma controller i i/o address read/write description 0000h r/w dma channel 0 current address 0001h r/w dma channel 0 current word count 0002h r/w dma channel 1 current address 0003h r/w dma channel 1 current word count 0004h r/w dma channel 2 current address 0005h r/w dma channel 2 current word count 0006h r/w dma channel 3 current address 0007h r/w dma channel 3 current word count 0008h r/w command/status register 0009h r/w dma request register 000ah r/w dma single bit mask register 000bh r/w dma mode register 000ch r/w dma clear byte pointer 000dh r/w dma master clear 000eh r/w clear mask register 000fh r/w dma write all mask register bit chips and technologies, inc. p r e l i m i n a r y revision 3.0 9-1
table 9-2. interrupt controller i i/o address read/write description 0020h write intc icw1 write intc ocw2, ocw3 read intc interrupt request register (iir) read intc in-service register (isr) read intc polling data byte 0021h write intc icw2 write intc icw3 write intc icw4 write intc ocw1 read intc interrupt mask register (imr) table 9-3. internal configuration registers i/o address read/write description 0022h w/o internal configuration register index (see table 9-4.) 0023h r/w internal configuration register data n i/o address maps address maps 9-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 9-4. index registers icr index read/write description 01h r/w dma wait-state control register 40h r/o version register 41h r/w channel environment register 42h ---- (reserved) do not write to this register 43h ---- (reserved) do not write to this register 44h r/w peripheral control register 45h r/o miscellaneous status register 46h r/w power management register 47h ---- (reserved) do not write to this register 48h r/w rom enable register 49h r/w ram write protect register 4ah r/w shadow ram enable register 1 4bh r/w shadow ram enable register 2 4ch r/w shadow ram enable register 3 4dh r/w dram configuration register 4eh r/w extended boundary register 4fh r/w ems control register 60h r/w laptop features 61h r/w fast video control 62h r/w fast video ram enable 63h r/w high performance refresh 64h r/w cas timing for dma/master table 9-5. timer counter registers i/o address read/write description 0040h r/w timer 0 count load/read 0041h r/w timer 1 count load/read 0042h r/w timer 2 count load/read 0043h w timer control word address maps i/o address maps n chips and technologies, inc. p r e l i m i n a r y revision 3.0 9-3
table 9-6. miscellaneous i/o registers i/o address read/write description 0061h r/w control/status port 0070h w real time clock index and nmi mask 0071h r/w real time clock data port 0092h r/w system control port table 9-7. dma page registers i/o address read/write description 0081h w dma channel 2 page register 0082h w dma channel 3 page register 0083h w dma channel 1 page register 0087h w dma channel 0 page register 0089h w dma channel 6 page register 008ah w dma channel 7 page register 008bh w dma channel 5 page register 008fh w refresh address page register table 9-8. interrupt controller ii i/o address read/write description 00a0h w intc icw1 w intc ocw2 w intc ocw3 r intc interrupt request register (iir) r intc in-service register (isr) r intc polling data byte 00a1h w intc icw2 w intc icw3 w intc icw4 w intc ocw1 r intc interrupt mask register (imr) n i/o address maps address maps 9-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 9-9. dma controller ii i/o address read/write description 00c0h r/w channel 0 base and current address 00c2h r/w channel 0 base and current word count 00c4h r/w channel 1 base and current address 00c6h r/w channel 1 base and current word count 00c8h r/w channel 2 base and current address 00cah r/w channel 2 base and current word count 00cch r/w channel 3 base and current address 00ceh r/w channel 3 base and current word count 00d0h r/w read status register/write command register 0 00d2h r/w write requrest register 00d4h r/w write single mask register bit 00d6h r/w write mode register 00d8h r/w clear byte pointer flip-flop 00dah r/w read temporary register/write master clear 0 00dch r/w clear mask register 00deh r/w write all mask register bits 00dfh r/w dma write all mask register bits table 9-10. coprocessor registers i/o address read/write description 00f0h w clear coprocessor busy 00f1h w not used in the 82c836 table 9-11. ems page registers i/o address read/write description 02x8h ? r/w ems page register, a21-a14 02x9h ? r/w ems page register, enable and a23-a22 02xah ? r/w ems page register select ? x = 0 or 1 depending on icr 4f bit 0. address maps i/o address maps n chips and technologies, inc. p r e l i m i n a r y revision 3.0 9-5
memory address map the following table identifies the memory addresses used in the 82c836. for more detailed information about memory addressing, refer to the ibm pc/at technical reference manual. table 9-12. memory address map i/o address read/write description 000000-09ffffh r/w ?? conventional ?? system ram 0a0000-0bffffh r/w video memory or shadow ram 0c0000-0effffh r/w bios extension or shadow ram 0f0000-0fffffh r/w rom or shadow ram 100000-fbffffh r/w extended or expanded memory fc0000-ffffffh r/w expanded memory (ems) fc0000-feffffh r/o bios extension image ff0000-ffffffh r/o rom image n memory address map address maps 9-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 10 configuration registers internal configuration registers (icrs) are accessed by addressing an index register at port 22h and immediately writing (or reading) data to (or from) port 23h. the 82c836 contains icrs at index values 01h, 40h - 4fh, and 60h - 64h. all icrs are read/write unless noted. to avoid unpredictable results, all reserved bits must be written as zero unless otherwise noted. the value read from a reserved bit is not defined and may vary unpredictably from one read to the next. table 10-1. index 01h ---- dma wait state control bit name description 7-6 ---- reserved. 5-4 16-bit dma wait-states these bits control the number of wait-states inserted during 16-bit dma transfers, as follows: 00 = one wait-state (default) 01 = two wait-states 10 = three wait-states 11 = four wait-states 3-2 8-bit dma wait-states these bits control the number of wait-states inserted during 8-bit dma transfers, as follows: 00 = one wait-state (default) 01 = two wait-states 10 = three wait-states 11 = four wait-states 1 dma xmemr extension in the ibm pc/at, the assertion of -xmemr is delayed by one dma clock cycle compared to -xior. this may not be desirable in some systems. 0 = enables delayed -xmemr function (default). 1 = starts -xmemr at the same time as -xior. 0 dma clock sel this bit allows the user to program the dma clock to operate at either busclk or busclk/2. the same dma clock drives both 8-bit and 16-bit operations. 0 = busclk/2 (default) 1 = busclk if bit 0 is changed during operation, an internal synchronizer controls the actual switching of the clock to prevent a short clock pulse from causing a dma malfunction. chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-1
table 10-2. index 40h ---- 82c836 version, read only bit name description 7-4 family type identifies specific part in pin-compatible family. scatsx denoted by 0001. 3-0 device revision code identifies revision level of the 82c836 silicon, starting with 0000. the 82c836b has revision code 0100; the 82c836a has code 0011. table 10-3. index 41h ---- channel environment bit name description 7 fast refresh this bit controls an improvement in hold timing to reduce total hlda time during refresh. up to 1% performance improvement possible. 0 = enable fast refresh (default) 1 = disable; follow revision 1 refresh timing this bit is intended to remain zero except for test purposes. 6 early ready enable allows external devices to assert ready during the first t2 after t1 to terminate the memory cycle after only two t-states. enables ?? early wait state ?? for local memory read not ?? claimed ?? by early ready. 1 = enable* 0 = disable (default) 5 lba enable allows external devices to assert lba (0ws pin) during the first t2 after t1 to prevent the 82c836 from starting a memory cycle. enables early wait state for local memory read not claimed by lba. 1 = enable* 0 = disable (default) if both early ready and lba are enabled, there will still be only one early wait state for unclaimed local memory reads. 4 bus convert enable enable conversion of 8-bit at bus reads into 16-bit reads so that a local cache, if present, can cache 16 bits at a time. 1 = enable 0 = disable (default) this feature does not apply to 8-bit at bus memory resources residing in the first 1mb. also, the usual at-compatible conversion of ?? even word ?? accesses into paired byte operations is not affected by this bit. this bit has no effect unless bit 6 is set. 3-2 busclk sel selects at bus clock. 00 = selects busclk as cxin/4 01 = selects busclk as cxin/5 (default) 10 = selects busclk as cxin/6 11 = (reserved) 1-0 refresh width these bits specify -xmemr pulse width during a refresh cycle. these pulse widths are derived from osc. the width of -xmemr directly affects the overall bus cycle time for refresh operations. 00 = 104ns 01 = 210ns 10 = 280ns (default) 11 = 350ns * bits 5 and 6 must remain zero if cpu pipeline mode is enabled. n configuration registers 82c386 chipset data sheet 10-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
index 42h and index 43h are reserved. index 44h controls whether peripherals are accessed on the xd-bus or sd-bus. the sdirh and sdirl sd-bus controls are affected by bits in this register. table 10-4. index 44h ---- peripheral control bit name description 7 ---- reserved. 6 video on the xd-bus this bit indicates whether or not a video controller is resident on the xd-bus. 0 = video controller is on the sd-bus. 1 = video controller is on the xd-bus. the i/o address ranges covered for the video controller are 0102h-0104h, 03b0h-03dfh, and 46e8h. video memory address range is 0a0000h through 0bffffh. the power-on default value of this bit is determined by the state of -dack2 (inverted) during power-on reset. -dack2 high causes this bit to default to zero. if the -dack2 strap option is used to denote something other than ?? video on x-bus,, ?? software (bios) must write this icr bit to the correct value before accessing the video controller. 5 game port on the xd-bus this bit specifies whether or not the game port is resident of the xd-bus. the i/o address range covered 0200h-0207h. 0 = game port on the sd-bus (default) 1 = game port on the xd-bus. 4 serial port channel 2 on the xd-bus specifies whether or not serial port 2 is resident on the xd-bus. the i/o address range is 02f8h-02ffh. 0 = serial port 2 on the sd-bus (default). 1 = serial port 2 on the xd-bus. 3 serial port channel 1 on the xd-bus specifies whether or not serial port 1 is resident on the xd-bus. the i/o address range is 03f8h-03ffh. 0 = serial port 1 on the sds-bus (default) 1 = serial port 1 on the xd-bus. 2 parallel port on the xd-bus specifies whether or not a parallel port is resident on the xd-bus. the address range covered 0378h-037fh. 0 = parallel port on the sd-bus (default) 1 = parallel port on the xd-bus. 1 hdc/fdc on the xd-bus specifies whether or not the hard drive and diskette drive controllers are resident on the xd-bus. the i/o address ranges covered are 01f0h-01f7h and 03f0h-03f7h, as well as dma channel 2 (-dack2) 0 = hdc/fdc on the sd-bus (default). 1 = hdc/fdc on the xd-bus. 0 coprocessor ready determines whether ready is controlled by the 82c836 or 80387sx during coprocessor accesses. if no coprocessor is present, the 82c836 always controls ready during coprocessor i/o cycles, regardless of the state of this bit. if a coprocessor is present and the readyo logic is not implemented, bios should set this bit to one. otherwise, the system will hang due to lack of ready as soon as post or other software tries to access the coprocessor. 0 = 80387sx generates ready (default) 1 = 82c836 generates ready note: memory resources on the xd bus can be rom or video ram. the only dma device allowed on the x d bus is the hdc/fdc. the bioses associated with video and/or hdc should be included in the -romcs decoding (icr 48h); they are not included in sdir decoding (icr 44h) for xd-bus peripherals. 10k pull-up resistors should be used on xd0-15 in systems that use xd-bus peripherals so read cycles from unused xd-bus addresses will receive 0ffh da ta. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-3
table 10-5. index 45h ---- miscellaneous status, read only bit name description 7 nmi inhibit this bit indicates the current state of the nmi inhibit bit of i/o port 70h, bit 7. bit 7 of i/o port 70h is write only. 0 = nmi enabled. 1 = nmi disabled (port 70 is default). 6 gatea20 from 8042 this bit indicates the current state of the gatea20 input from the 8042 keyboard controller. 5 busy to cpu this bit indicates the current state of the latched busy signal to the 80386sx. 0 = busy signal low. 1 = busy signal high. 4 internal rtc enabled this bit indicates the state of the -exrtc (-dack5) pin during reset. 0 = external rtc used (xd bus). 1 = internal rtc used. 3 -na/-stcyc select normally the -na pin is used as an -na and/or -adrl signal. for external cache support, it can be changed to operate as a cpu cycle start (-stcyc) and/or address latch (-adrl) signal. 0 = -stcyc/-adrl function 1 = -na/-adrl function the state of this bit is determined by the state of -dack3 during reset. -dack3 should be pulled up if -na goes to the cpu. 2-0 sense lines 2-0 these lines (2-0) sense the power-up state of dack lines (2-0), respectively (noninverted). these lines can be used for power-up setup parameters. -dack2 (inverted) also determines the power-up state of icr 44h bit 6. 0 = corresponding dack line pulled low. 1 = corresponding dack line pulled high. a 4.7k ohm resistor is recommended for the pull-up or pull-down. index 46h controls sleep mode and procclk frequency for power conservation. table 10-6. index 46h ---- power management bit name description 7 sleep enable this bit enables sleep mode. if this bit is set, sleep mode will be entered upon execution of a halt instruction. an interrupt (intr or nmi) will terminate sleep mode until a subsequent halt; a dma or refresh will terminate sleep mode temporarily, then return to sleep mode upon completion of the dma or refresh. 0 = sleep mode disabled (default). 1 = sleep mode enabled. n configuration registers 82c386 chipset data sheet 10-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 10-6. index 46h ---- power management (continued) bit name description 6 aux parity disable this bit, when set, is an alternate parity error clear and disable; in addition to port 61h bit 2. either this bit (if set), or port 61h bit 2 (if set), will clear the internal parity error latch and prevent further parity error detection. 0 = enable parity checking (default). port 61h bit 2 must also be zero to enable parity checking. 1 = parity error clear and disable, independent of port 61h bit 2. 5 high shadow ram enable this bit causes memory accesses in the ?? high rom ?? area (see icr 4eh, bit 4) to be remapped into shadow ram at the address obtained by forcing a23-20 to 0h. this feature is useful in laptops in which shadow ram is used for bios, and it is desired to have cpu instruction fetches following cpu reset go to 0ffff0h in the shadowed bios area instead of going to rom at fffff0h (cpu reset without xrst is generally used to return to real mode from protected mode). do not set this bit unless shadow ram has been enabled in the translated address range. scatsx will not perform a rom or at bus access in response to a translated high rom read or write, regardless of other icr bit settings. shadow ram write protection, if enabled, applies to translated high rom writes as well as other types of writes. ems has no effect on the translation, even if the translated address happens to fall within the internal ems page frame; the high rom translation bypasses the ems mechanism. an early wait state always occurs on translated high rom accesses. master accesses to high rom are affected by this bit in the same way as cpu accesses. 0 = no high rom translation (default) 1 = enable high rom translation to shadow ram this bit is always cleared by a logic low level on pwrgood, even if stand-by mode is enabled (see icr 60h). consequently, this bit cannot affect high rom accesses immediately following system reset via pwrgood. 4 ---- reserved. 3-2 run freq these bits select the frequency of the procclk signal to the cpu when in normal run mode. 00 = cxin (default) 01 = cxin/2 10 = cxin/4 11 = cxin/8 1-0 sleep freq these bits select the frequency of the procclk signal to the cpu when in sleep mode. 00 = stopped (default). see icr 64h bits 4-3. 01 = cxin/2 10 = cxin/4 11 = cxin/8 note: refresh, dma and master cycles always run at full speed, procclk = cxin, regardless of bits 3 -0. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-5
index register 47h is reserved. index register 48h determines the address ranges included in the -romcs output. the power-on default address range is 0f0000h-0fffffh. the range from fc0000h to ffffffh may also be enabled, depending on icr 4eh bit 4 and icr 46h bit 5. the -dack7 pin is used during reset to specify the width of the rom accessed with the -romcs signal. if a 4.7k pull-down is placed on -dack7, accesses to rom will always be 16-bits wide (two roms are required), and -memcs16 will be asserted for all rom cycles. a 4.7k pull-up is needed on -dack7 for 8-bit wide rom. each bit enables or disables -romcs for the address range specified as follows: 1 = enable rom 0 = disable rom do not enable rom and shadow ram in the same range at the same time. table 10-7. index 48h ---- rom enable bit description 7 0f8000h-0fffffh rom enable. default = 1 6 0f0000h-0f7fffh rom enable. default = 1 5 0e8000h-0effffh rom enable. default = 0 4 0e0000h-0e7fffh rom enable. default = 0 3 0d8000h-0d8fffh rom enable. default = 0 2 0d0000h-0d7fffh rom enable. default = 0 1 0c8000h-0cffffh rom enable. default = 0 0 0c0000h-0c7fffh rom enable. default = 0 n configuration registers 82c386 chipset data sheet 10-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
index 49h is used to write protect ram in the address ranges specified as follows: 1 = read only 0 = read/write default for all bits is 0. table 10-8. index 49h ---- ram write protect bit description 7 0f8000h-0fffffh ram read only 6 0f0000h-0f7fffh ram read only 5 0e8000h-0effffh ram read only 4 0e0000h-0e7fffh ram read only 3 0d8000h-0dffffh ram read only 2 0d0000h-0d7fffh ram read only 1 0c8000h-0cffffh ram read only 0 0c0000h-0c7fffh ram read only index 4ah controls whether shadow ram is enabled or disabled in the 16kb address ranges specified as follows: 1 = enable ram 0 = disable ram default for all bits is 0. table 10-9. index 4ah ---- shadow ram enable 1 bit description 7 0bc000h-0bffffh ram enable 6 0b8000h-0bbfffh ram enable 5 0b4000h-0b7fffh ram enable 4 0b0000h-0b3fffh ram enable 3 0ac000h-0affffh ram enable 2 0a8000h-0abfffh ram enable 1 0a4000h-0a7fffh ram enable 0 0a0000h-0a3fffh ram enable 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-7
index register 4bh controls whether shadow ram is enabled or disabled in the 16kb address ranges specified as follows: 1 = enable ram 0 = disable ram default for all bits is 0. table 10-10. index 4bh ---- shadow ram enable 2 bit description 7 0dc000h-0dffffh ram enable 6 0d8000h-0dbfffh ram enable 5 0d4000h-0d7fffh ram enable 4 0d0000h-0d3fffh ram enable 3 0cc000h-0cffffh ram enable 2 0c8000h-0cbfffh ram enable 1 0c4000h-0c7fffh ram enable 0 0c0000h-0c3fffh ram enable index register 4ch controls whether shadow ram is enabled or disabled in the 16kb address ranges specified as follows: 1 = enable ram 0 = disable ram the default for all bits is 0. table 10-11. index 4ch ---- shadow ram enable 3 bit description 7 0fc000h-0fffffh ram enable 6 0f8000h-0fbfffh ram enable 5 0f4000h-0f7fffh ram enable 4 0f0000h-0f3fffh ram enable 3 0ec000h-0effffh ram enable 2 0e8000h-0ebfffh ram enable 1 0e4000h-0e7fffh ram enable 0 0e0000h-0e3fffh ram enable note: do not enable rom and shadow ram in the same address range at the same time; do not enable sh adow ram when using memory configuration #03h (640k + 384k). n configuration registers 82c386 chipset data sheet 10-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 10-12. index 4dh ---- dram configuration bit description 7 cas wait state allows an additional t-state (two procclk cycles) to be inserted on all local memory accesses. the added t-state is inserted during the cas active interval, extending the width of the cas pulse. 0 = no added wait state (default) 1 = wait state enabled 6 ras timeout disables the ras timeout feature. 0 = ras timeout enable (default) 1 = ras timeout disabled 5 cas wait state for read allows the cas wait state (bit 7 above) to be inserted on local memory reads, but not on writes. 0 = wait state controlled by bit 7 above (default) 1 = cas extend wait state enabled on memory read, regardless of bit 7; wait state for write still controlled by bit 7. 4-0 cfg4-0 these bits specify the dram configuration as described in section 5, system interface, subsection titled dram interface. the default value after reset is 00001 (512kb total dram). table 10-13. index 4eh ---- extended memory boundary bit name description 7 ras encode enable this bit changes the four -ras lines into three encoded -ras lines and one -ras timing line. these four lines are used with an external 3-8 decoder to support eight banks of dram. 0 = -ras encode disabled (default) 1 = -ras encode enabled 6 mra enable enables the ?? multiple ras active ?? mode for higher system performance. 0 = single ras active mode (default) 1 = multi ras active mode. also enables multiplexed dreqs and encoded dacks 5 ram disable 040000h-09ffffh this bit disables the 82c836?s internal dram controller for accesses in the range. 040000h-09ffffh. these accesses are directed to the i/o channel. 0 = enables 040000h-09ffffh dram range (default). 1 = disabled 040000h-09ffffh dram range. 4 high rom enable this bit should be set to one for pc/at compatibility (see also icr 46h bit 5, high shadow ram enable). 0 = enable fc0000h and above (256k) as rom (default) 1 = enable fe0000h and above (128k) as rom. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-9
table 10-13. index 4eh ---- extended memory boundary (continued) bit name description 3-0 extended boundary these bits specify the upper boundary of memory within the total memory defined by internal configuration register 4dh. memory residing above this boundary is accessible only via ems. bits 3 2 1 0 extended memory boundary 0 0 0 0 no limit (default); entire dram accessible 0 0 0 1 1mb (i.e., no extended memory) 0 0 1 0 1.25mb 0 0 1 1 1.5mb 0 1 0 0 2mb 0 1 0 1 3mb 0 1 1 0 4mb 0 1 1 1 5mb 1 0 0 0 7mb 1 0 0 1 8mb 1 0 1 0 9mb 1 0 1 1 10mb 1 1 0 0 11mb 1 1 0 1 12mb 1 1 1 0 13mb 1 1 1 1 15mb table 10-14. index 4fh ---- ems control register bit name description 7 ems address translation enable this bit enables ems memory access. 0 = ems is disabled (default). 1 = ems is enabled . 6 ems i/o enable this bit enables access to the ems i/o ports. 0 = ems i/o port access is disabled (default). 1 = ems i/o port access is enabled. 5-1 ---- reserved. 0 i/o base this bit specifies which i/o ports are used to read or write ems page registers. 0 = i/o ports 0208h, 0209h, and 020ah (default). 1 = i/o ports 0218h, 0219h, and 021ah. n configuration registers 82c386 chipset data sheet 10-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
the purpose of index 60h is to allow dram refresh to continue during power-down. consequently, bits 7-3 are preserved during power-down instead of cleared by pwrgood. to initialize this icr to its default value, a logic low level on the power sense (mfp5) input is used while pwrgood is low. table 10-15. index 60h ---- laptop features bit name description 7 cas-before-ras refresh enable 0 = ras only refresh (default) 1 = cas before ras refresh 6 stand-by refresh enable (also known as stand-by mode) this mode allows local dram refreshing to continue during power-down. no refresh address is generated during power-down, so cas-before-ras refresh should be enabled and drams that support cas-before-ras refresh should be used. stand-by refresh relies on the 32khz input clock (mfp4 pin), which isn?t available with external rtc (mfp4 becomes irq8). consequently, stand-by refresh cannot be used with external rtc. 0 = no refresh during power-down (default) 1 = refresh continues during power-down this bit, when set to one, has the following additional effects: icr 4dh bits 4-0 (memory configuration) are preserved during power-down. icr 4eh bit 6 (mra enable) is preserved during power-down. dack signals are no longer sampled following pwrgood rise. pwrgood fall (powering down) takes effect only after stand-by refresh is operational to maintain refresh continuity. for assured recovery from potential lockup conditions following initial power turn-on or software malfunction, the 82c836b contains a built-in 32khz based timeout and external rtc interlock to clear this bit automatically under abnormal conditions. pwrgood can then take effect in the normal manner without standby mode 5-4 stand-by refresh interval allows reduced power consumption for stand-by refresh during power- down via reduced dram refresh rate if compatible drams are used. the reduced refresh rate takes effect only during power-down and only if stand-by refresh is enabled. 00 = 15 m s (default; half cycle of 32.768khz input clock) 01 = 61 m s (2 cycles of 32.768khz input clock) 10 = 122 m s (4 cycles of 32.768khz input clock) 11 = 244 m s (8 cycles of 32.768khz input clock) 3 refresh time base (read only) indicates whether or not the system has switched from stand-by refresh to normal. if stand-by mode is enabled, the system switches from 14.3mhz refresh timing to 32khz timing during power-down. when power comes back up, the bios must reprogram timer channel 1 (see section 6, programmable interval timer ) to get refresh request running again. the 82c836 then switches back to 14.3mhz based refresh. bios should not try to access dram until the switch back to 14.3mhz timing has occurred. the switching of the refresh time base is done in a double-synchronized manner to prevent any lost or aborted refresh cycles. 0 = 14.3mhz based refresh 1 = 32khz based refresh 2-0 ---- reserved. write as 0. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-11
index register 61h controls the following special modes for video access: fast 8-bit i/o access ---- cycle timing equivalent to 16-bit cycles, but using only the low byte of the data bus for data transfer. fast 8-bit memory access ---- cycle timing equivalent to 16-bit cycles, but using only the low byte of the data bus for data transfer. forced -memcs16 for 16-bit memory access. 82c836b asserts -memcs16 and performs a 16-bit cycle, eliminating the need for equivalent logic in the video subsystem. in all cases, iochrdy can be used to insert bus wait states. table 10-16. index 61h ---- fast video control bit name description 7-6 ---- reserved. write as 0. 5 i/o 3d0-3dfh enable 0 = normal operation (default) 1 = fast 8-bit i/o 4 i/o 3c0-3cfh enable 0 = normal operation (default) 1 = fast 8-bit i/o 3 i/o 3b0-3bbh enable the parallel port i/o address range, 3bc-3bfh, is not affected by this bit. 0 = normal operation (default) 1 = fast 8-bit i/o 2 fast 8-bit i/o enable enables the fast 8-bit i/o mode for i/o accesses in the ranges selected via bits 3, 4, and 5 above. bits 3, 4, and 5 have no effect if bit 2 is zero. 0 = normal operation (default) 1 = fast 8-bit i/o 1 force memcs16. 0 = normal operation (default) 1 = 82c836b asserts -memcs16 and performs 16-bit cycle timing and protocol for all memory accesses in the ranges selected via icr 62h. do not set both bit 1 and bit 0 to one at the same time. 0 fast 8-bit memory enable enables the fast 8-bit mode for memory accesses in the ranges selected via icr 62h. 0 = normal operation (default) 1 = fast 8-bit memory access. index 62h enables the memory address ranges selected below for either fast 8-bit memory timing or forced memcs16 mode, depending on the bit settings in icr 61h. 0 = range not selected (default) 1 = range selected n configuration registers 82c386 chipset data sheet 10-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 10-17. index 62h ---- fast video ram enable bit description bit description 7 0bc000h - 0bffffh 3 0ac000h - 0affffh 6 0b8000h - 0bbfffh 2 0a8000h - 0abfffh 5 0b4000h - 0b7fffh 1 0a4000h - 0a7fffh 4 0b0000h - 0b3fffh 0 0a0000h - 0a3fffh table 10-18. index 63h ---- high performance refresh bit name description 7 hidden refresh enable causes system-initiated refresh cycles to be performed by inserting cpu wait states as needed instead of using hold/hlda protocol. in a cache-based system, this allows the cpu to continue performing cache read hit cycles simultaneously with a refresh cycle in local memory and on the at bus. if the cpu tries to access local memory or the at bus while a hidden refresh cycle is in progress, the cpu is delayed via wait states until the refresh is completed. 0 = normal hold/hlda refresh (default) 1 = hidden refresh 6 refresh on idle this bit causes hidden refresh cycles (if enabled) to be initiated only following a cpu idle state (no -ads since last -ready, and hlda inactive). depending on system workloads, waiting for cpu idle states may slightly increase the probability of successfully hiding refresh cycles during cache read hits. 0 = hidden refresh doesn?t wait for cpu idle (default) 1 = hidden refresh waits for cpu idle (or timeout) if no cpu idle states occur within the normal time limit between refresh cycles, then refresh is initiated after the current cpu cycle terminates (-ready), without waiting for a cpu idle state. this insures dram refresh requirements will be met even if the cpu is unusually busy. 5 at refresh disable allows at bus refresh to be disabled during hidden refresh. the total time needed to perform a hidden refresh is greatly reduced in this mode, since local memory requires far less time for a refresh than the at bus. the result is a significant performance benefit in cache-based systems if at bus refresh is not needed (non-cache systems will not benefit as much beause of the performance effect of running exclusively in nonpipeline mode). 0 = at refresh enabled during hidden refresh (default) 1 = at refresh disabled during hidden (non-hlda) refresh -ref and -memr are not generated during hidden refresh if at refresh is disabled. however, any refreshes performed while hlda is active for dma or master cycles are still performed in the normal manner, including refresh on the at bus. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-13
table 10-18. index 63h ---- high performance refresh (continued) bit name description 4-3 hidden refresh timing adjusts hidden refresh timing according to cpu speed. refresh timing during hlda is not affected. 00 = reserved 01 = 16mhz cpu speed (default) 10 = 20mhz or 25mhz cpu speed 11 = reserved 2 refresh delay enables extra delay from one refresh to the next when an add-on card bus master holds -ref active long enough to cause multiple back-to-back refresh cycles. as in a pc/at, refresh address remains the same for each subsequent refresh cycle occurring while -ref remains continuously asserted. 0 = one microsecond delay from -xmemr active to next -xmemr active for multiple refresh in master mode (default) 1 = no delay added; same timing as in revision 1. normally, this bit should remain zero to prevent subsequent refreshes from starting prematurely when a master keeps -ref asserted longer than necessary for one refresh cycle (or when -ref has unusually long rise time due to insufficient pull-up resistance). 1 ---- reserved. write as 0. 0 write through disable in cache-based scatsx systems, memory writes normally go directly to dram without any delay as compared to non-cache systems; local memory writes cannot be ?? claimed ?? by the cache controller. this bit changes memory write protocol so that memory writes can be claimed by external logic i.e., no write cycle performed in memory. in a cache-based system, this feature generally will be useful only for diagnostic purposes. this features may also be useful in certain high-performance, non-cache systems that rely on dynamic cycle claiming on writes as well as reads. 0 = normal write-through protocol (default); no early wait state 1 = write-through disable; writes can be externally claimed; early wait state inserted. only local memory writes are affected by this bit. local memory reads and all at bus memory or i/o accesses are already subject to cycle claiming (icr 41h bits 5 and 6). if this bit is set to one, icr 41h bit 5 or 6 (or both) should also be set to one. for timing reasons, hidden refresh mode of index 63h requires that the cpu operate exclusively in nonpipelined mode; the -na signal to the cpu must be held high continuously. the -na output from scatsx is not affected (if scatsx is programmed for -stcyc mode on the na/stcyc pin, the -stcyc pulse is delayed until the hidden refresh is complete). the cpu address bus remains available to the cpu during hidden refresh, so at bus refresh must either be turned off (see bit 5 in icr 63h) or the at bus refresh address must be provided by other external logic. the 82c835a cache controller is designed to provide the at bus refresh address during hidden refresh. scatsx continues to generate -ref and -xmemr during hidden refresh if at bus refresh is enabled, and the 82c835 can be programmed to use these signals to generate the at bus refresh address. n configuration registers 82c386 chipset data sheet 10-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
timing considerations also require all externally claimed cycles to have zero wait states. for cycles claimed via early ready, as with the 82c835 cache controller, this will always be the case automatically. cycle claiming via -lba is effectively unusable when hidden refresh is enabled unless -ready is asserted on the same t-state as -lba. if hlda is already active for a dma or master cycle, normal refresh cycles occur as needed without waiting for hlda to end. the refresh requests internally sent to the hidden refresh logic are reduced accordingly. also, during sleep mode, normal hold/hlda refresh is performed instead of hidden refresh. table 10-19. index 64h ---- cas timing for dma/master bit name description 7 respond during reset determines whether or not the 82c836b will perform a normal cycle in response to cpu activity occurring while cpu reset is active. the cpu can initiate one or more bus cycles after cpurst has been asserted. the 82c836b can either ignore these cycles or respond normally as if no cpu reset is in progress. 0 = ignore cpu cycles starting after cpurst goes active (default) 1 = respond as usual to cpu cycles starting after cpurst goes active. 6-5 ---- reserved. write as 0. 4-3 stopped clock sleep phase these bits select the exact phase within a t-state in which procclk stops during sleep mode when a sleep frequency of zero has been selected. this will allow maximum flexibility with static cpus. zero-frequency sleep mode should be used only with a static cpu. 00 = procclk low, 1st half of t-state (default) 01 = procclk low, 2nd half of t-state 10 = procclk high, 1st half of t-state 11 = procclk high, 2nd half of t-state 2-0 cas delay for dma/master write these bits determine when cas is asserted during dma or master write cycles to local memory. cas assertion during reads is not affected. the minimum delay from valid column address to assertion of cas is one procclk. up to four additional procclks can be added, for a maximum of five procclks total. 000 = no added delay 001 = 1 procclk delay added 010 = 2 procclks delay added 011 = 3 procclks delay added (default) 100 = 4 procclks delay added 101 = reserved 110 = reserved 111 = reserved for 25mhz operation, 011 should be optimum. for 20mhz operation, 010 should be optimum. for 16mhz operation, 001 should be optimum. the timing of cas is most critical relative to valid write data and parity. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-15
the only known case where index register 64h bit 7 makes any difference in system operation is when running certain diagnostic programs that use cpurst on a system having an 82c835 cache controller, but with cache operation disabled (cpu reset without xrst is often used to return the cpu to real mode from protected mode). the 82c835 needs to see ready in response to every ads, including ads pulses occuring during cpu reset. setting this bit to one allows the 82c836b to finish every cpu cycle started during cpu reset, including assertion of ready. this bit might need to be zero if software attempts to perform a cache read miss (cache enabled) or memory write operation during cpu reset. normally, however, software will halt the cpu or execute a ?? jump to self ?? loop (cache read hits) while waiting for cpu reset to take effect. thus, it should be safe always to set bit 7 to one. ems page registers this section lists the bit assignments for the three i/o ports used to access the four ems page registers. i/o port 208h (or 218h) accesses bits 21 through 14 of the address of the 16kb target page to be mapped into the corresponding page window in the 64kb remappable address range. the page register accessed by this port is selected by port 20ah (or 21ah). table 10-20. port 208h ---- target page address bit description bit description 7 a21 of target page address 3 a17 of target page address 6 a20 of target page address 2 a16 of target page address 5 a19 of target page address 1 a15 of target page address 4 a18 of target page address 0 a14 of target page address n configuration registers 82c386 chipset data sheet 10-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
port 209h (0r 219h) accesses bits 23 and 22 of the address of the 16kb target page mapped into the selected page window of the 64kb remappable address range. the page register accessed by this port is selected by port 20ah (or 21ah). table 10-21. port 209h ---- page enable bit name description 7 page enable ?? page disable ?? means that the page window in the 64kb remappable address range is not remapped but is treated as ordinary non-ems memory. 1 = page enable 0 = page disable. 6-2 ---- reserved. 1 ---- a23 of target page address 0 ---- a22 of target page address table 10-22. port 20ah ---- ems page select bit name description 7 auto-increment enables auto-incrementing of the page register selection index (bits 1-0 in this register) whenever port 208h (or 218h) is read or written. incrementing does not occur on access to port 209h (or 219h). 16-bit i/o may be used to read or write both ports 208h and 209h (or 218h/219h) simultaneously, with or without auto-increment. 1 = enable auto-incrementing 0 = disable auto-incrementing 6 page frame base address determines whether the 64kb remappable address range (page frame) begins at 0d0000h or 0e0000h. 0 = 0d0000h (default) 1 = 0e0000h 5-2 ---- reserved. 1-0 index selects one of the four ems page registers for access via ports 208h and 209h (or 218h and 219h). can be programmed for automatic incrementing via bit 7 above. page registers are numbered in order from 00 through 11 (binary), and the associated page window addresses in the 64kb remappable address range follow in ascending order. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-17
port 61h controls several system-level functions. the port can be accessed through any odd i/o port address from 61h through 6fh. table 10-23. port 61h ---- control port/status bit name description 7 parity error (read only) this bit (if 1) indicates that a parity error has been detected during a local memory read. causes nmi if port 70h bit 7 is 0. 6 iochck (read only) this bit (if 1) indicates an i/o channel check has occured (usually a parity error) on the system i/o channel. causes nmi if port 70h bit 7 is 0. 5 tmr 2 out (read only) this bit returns the condition of the timer 2 output (speaker tone). 4 refresh detect (read only) this bit toggles on each refresh cycle. 3 chck dis (read/write) this bit clears and disables the internal i/o channel check detection latch. 1 = latch clear and disable. bit 6 still responds to iochck (unlatched) but does not cause nmi. 0 = enable i/o channel check detection. 2 parity disable (read/write) this bit, if set, clears and disables the internal parity error detection latch. 1 = parity error latch clear and disable. 0 = parity checking enable (default), if icr 46h bit 6 is also zero. 1 spkr data (read/write) this bit gates the output of channel 2 of the timer/counter (speaker tone). 1 = output is enabled, i.e., speaker tone on. 0 = output is forced low (default) 0 tmr 2 gate (read/write) this bit gates the clock input for timer channel 2 (speaker tone). 1 = channel 2 timer clock enabled. 0 = channel 2 timer clock disabled (default). n configuration registers 82c386 chipset data sheet 10-18 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
port 70h is used to access the real-time clock (rtc) and its cmos ram. it can also block nmis from going to the cpu. bits 6-0 are not used when the external rtc option is selected. table 10-24. port 70h ---- rtc/cmos index and nmi mask bit name description 7 nmi mask (write only) this bit masks the generation of nmis. if an nmi causing condition (see port 61h) exists at the time this bit is cleared, the nmi is sent to the cpu. 0 = enable nmi 1 = inhibit nmi (default) 6-0 rtc index bits 6:0 these bits specify the index (address) for accessing the 128 locations in the rtc and cmos ram (114 user ram, 14 rtc registers). port 71h accesses the indexed location. if an external real-time clock is used, ports 70h and 71h (except port 70h bit 7) are inoperative in the 82c836 and should be implemented externally. port 71h is used to transfer data to and from the internal real-time clock and cmos ram. the rtc register is selected by bits 6:0 of i/o port 70h as described earlier. table 10-25. port 71h ---- rtc/cmos data bit description 7-0 rtc data bits 7:0. 82c386 chipset data sheet configuration registers n chips and technologies, inc. p r e l i m i n a r y revision 3.0 10-19
port 92h is used as a fast alternative to gating a20 and resetting the cpu, rather than using the 8042 keyboard controller. this register is compatible with ibm ps/2 architecture. table 10-26. port 92h ---- system control bit name description 7-2 ---- reserved. 1 alt gatea20 allows address bit 20 to be compatible with the 8088 and 8086 at address ffff:10h and above. either a 1 in this bit or a high logic level on the gatea20 signal from the 8042 causes moda20 to follow cpu a20. to force moda20 low during cpu cycles, this bit must be zero and the gatea20 input signal must also be low. 0 = moda20 is forced low (8088 compatible). 1 = moda20 follows address bit a20 from cpu. 0 alt cpu reset a 0-to-1 transition causes a reset pulse on the cpurst pin to reset the cpu. there is a minimum delay of 6.72 microseconds before the reset pulse begins. this bit retains its state following cpu reset so the bios can determine why the cpu reset occured. the main reason for resetting the cpu alone is to return from protected mode in an 80286-compatible manner. n configuration registers 82c386 chipset data sheet 10-20 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 11 system timing relationships this section contains timing diagrams for all the major timing sequences in an at-compatible scatsx system. the diagrams emphasize the functional timing relationships between signals (i.e., what conditions cause the various timing events). for clarity, propagation delays and rise/fall times are either not shown or not drawn to scale. each diagram is accompanied by explanatory notes describing important aspects of the timing sequence. cpu access to at-bus figure 11-1 shows a bus convert read or write. -cmd refers to the following possibilities: -xmemr for a memory read cycle -xmemw for a memory write cycle -xior for an i/o read cycle -xiow for an i/o write cycle -lomegcs is generated during memory cycles in which the memory address is in the first 1mb of address space i.e., 0-0fffffh. the only intended use of -lomegcs outside the 82c836 is to enable the -smemr and -smemw drivers, allowing -smemr to be asserted if -xmemr is asserted, or -smemw if -xmemw is assererted. if the cycle is a memory read in an address range allocated for on-board rom, -romcs is asserted at the same time as -xmemr ( ?? same time ?? here means on the same clock edges, neglecting propagation delays). chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-1
figure 11-1. cpu access to at-bus n cpu access to at-bus system timing relationships 11-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
the delay from ale to the start of command, and the width of the command, depend on the type of cycle, as shown in the following table. table 11-1. delays from ale to start command in busclk cycles cycle type ale:cmd cmd width memory access to 16-bit resource 0 2.0 i/o access to 16-bit resource 0.5 1.5 memory or i/o to 8-bit resource 0.5 4.5 figure 11-1 depicts a command width of 2.5 cycles of busclk and a cmd delay of 0.5 cycle, a combination that never actually occurs unless -0ws is asserted. if the cmd delay is 0.5 cycle of busclk, the default command width will always be either 1.5 or 4.5 cycles of busclk. during bus conversions (which can occur only when accessing an 8-bit resource), the command inactive delay between the two bus cycles is always 1.5 cycles of busclk. it is the resource type (8-bit or 16-bit), not data transfer size, that determines cycle timing. for example, an 8-bit access to a 16-bit resource (-memcs16 and/or -iocs16 asserted) follows the 16-bit timing shown above. -memcs16 and -iocs16 timing is shown in figure 11-2. figure 11-2. -memcs16 and -iocs16 timing system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-3
for the 82c836, the first useful t-state of each cpu cycle is either t1p, or the first t2 after t1 (i.e., the t-state in which -ads changes from low to high). this t-state is referred to as ?? ts ?? (t-start) and is directly equivalent to the ts state in 80286-based systems. the delay from the middle of ts to the rising edge of ale is variable, depending on the phase and frequency relationship of busclk to procclk. although busclk is derived from (and therefore synchronous with) procclk, the exact phase can still vary from one bus cycle to the next, especially if busclk = procclk/5 or procclk/6. the minimum delay from mid-ts to ale rise is as follows: 1.0 cycle of procclk if busclk = cxin/4 1.5 cycles of procclk if busclk = cxin/5 2.0 cycles of procclk if busclk = cxin/6 the minimum delay from command rise to -ready fall is one cycle of procclk in all cases. -ready, in turn, is always synchronized to the last t2 or t2p of the bus cycle. bus conversion always begin with moda0 forced low for the first at bus cycle, then forced high for the second cycle. this is true for the force bus convert mode as well as normal bus conversions. normal bus conversion occurs on any cpu-generated memory or i/o read or write in which the cpu is requesting 16 bits of data to or from an 8-bit resource at an even memory or i/o address. (if the address is odd, the cpu itself automatically performs two separate byte transfers for a word operand.) if no bus conversion is needed (i.e., only a single at bus cycle is needed), there will be only one command pulse. end-of-cycle timing then begins at the end of the first command pulse instead of the second one. moda0 tracks cpu a0 (-ble), but is still latched during each ts (transparent during the first half of ts). cpu operation during at bus cycle is always nonpipelined, as shown in figure 11-3, if the -na output from the 82c836 is connected to the -na input on the cpu. however, the 82c836 -na signal can be used for other purposes; and the cpu -na input can be tied low or high, or controlled by other external logic. in such cases, it is possible for the cpu to operate in pipelined mode during an at bus cycle, resulting in the following changes in the timing relationships: the last state of the cycle can be a t2p instead of t2, in which case the next t-state will be t1p, with a new cpu cycle starting immediately (if the final state is t2, then the earliest that a new cycle can start is the first t2 after t1). -na timing is affected as shown in figure 11-3. cpu address no longer remains valid throughout the cycle, so it must be latched externally in order to meet sa-bus requirements. if 74f543 latches are used, -na from the 82c836 can be used as a latch enable (a 74f244 and 74f373 can be used instead of a 74f543 if desired). n cpu access to at-bus system timing relationships 11-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-3. -na/-stcyc timing system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-5
cpu accesses to the at bus, whether memory or i/o, read or write, can be ?? claimed ?? by external logic using the early ready or lba modes. if either of these modes is enabled, but an at bus access is not claimed by external logic, the 82c836 will perform a normal at bus cycle as shown in the diagram, except for one minor timing difference: one additional procclk cycle is inserted in the delay from mid-ts to ale. in effect, the 82c836 waits unit the end of ts insead of the middle to decide whether or not it should perform an at bus cycle. sdirl and sdirh typically are either both low or both high. during dma or master cycles, however, byte swapping may require one of these signals to be low while the other remains high. the default state during bus idle periods is both signals high. -8042cs and -rtccs (mfp5 with external rtc), if asserted, follow -lomegcs timing; namely, they are updated at the start of each ts and remain latched until the next ts state or hlda assertion. interrupt acknowledge cycles are treated as i/o reads from an 8-bit resouce, except that ale and command are not generated, and the read data is an interrupt vector number originating from the interrupt controller section of the 82c836. halt cycles result in assertion of -ready, but no command is generated on the at bus. shutdown cycles result in the assertion of both -ready and cpurst. shutdown is used intentionally by some software programs, especially on 80286-based systems, to trigger a cpu reset and thereby bring the cpu out of protected mode. cpu reset doesn?t necessarily result in system reboot; in at-compatible architectures, certain designated locations in cmos ram are used by the bios to determine how the bios will respond to the cpu reset. the bios can be instructed to return control to a resident real mode program rather than reboot the operating system. other than shutdown, the conditions causing the 82c836 to reset the cpu include: fast cpu reset via port 92h (ps/2 compatible). cpu reset via the 8042 keyboard controller (at-compatible). hardware system reset via pwrgood (also causes xrst). memory write operations to an area programmed as eprom (-romcs) result in write cycles on the at bus. -xmemw is generated. -romcs remains inactive (high) during write operations. memory writes to write-protected shadow ram go nowhere i.e., normal dram write timing is followed except -cas is suppressed. no cycle is generated on the at bus. -memcs16 and -iocs16 timing figure 11-4 describes the timing relationships for -memcs16 and -iocs16. in most at-compatible architectures, -memcs16 will be an unlatched decode of the high-order unlatched address bits, ua17-23. similary, -iocs16 will be an unlatched decode of the latched address bits, sa0-19 (possibly gated with the i/o command signal). n cpu access to at-bus system timing relationships 11-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
when an attached memory resouce detects an address in its assigned range, it should assert -memcs16. when an attached i/o resource detects an address in its assigned range, it should assert -iocs16. since there is no way for a device on the at bus to know whether the cycle is a memory access or i/o access prior to a command signal going active, it is possible for -iocs16 and -memcs16 both to be asserted simultaneously by different at bus add-on cards. as previously shown in figure 11-1, the 82c836 (via -na) latches address bits 1-23 on the at bus before the start of ale, and keeps the address latched until after the end of the command pulse. moda0 also follows the same timing, except for the low to high transtion after the first cycle of a bus conversion. the 82c836 requires -memcs16 to be valid at the end of ale i.e., from slightly before the falling edge of ale until slightly after ale falls. the 82c836 samples -iocs16 on the first rising edge of busclk after i/o command goes active (low), -iocs16 must remain valid until the end of the i/o command. although -memcs16 and -iocs16 normally are asserted by 16-bit resources on the at bus, the 82c836 can assert either or both of these signals in the following cases: during on-board rom read, if on-board rom is 16 bits wide. during cpu, dma or master access to on-board dram. during access to ems i/o ports 2x8h and/or 2x9h (where x is programmable as either 0 or 1). a byte access to either port, or a word access at i/o address 2x8h, results in assertion of iocs16. these two ems i/o ports operate as a 16-bit i/o resource; data transfer to or from 2x9h always uses d8-15 and/or xd8-15. figure 11-4. -memcs16 and -iocs16 timing system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-7
iochrdy and ows figure 11-5 shows the effect of iochrdy and -0ws during cpu accesses to the at bus. if iochrdy and -0ws both remain high, the command width is determined by the defaults listed earlier. the default command timing is represented by the dashed lines. iochrdy can increase the command width, while 0ws can reduce it. iochrdy is first checked at time a, one busclk before the default end of command (b). detection of iochrdy low at time a causes the command to remain active for an additional busclk. iochrdy is sampled again on each successive rising edge of busclk until it is detected high. the command ends exactly one busclk after iochrdy is detected high. -0ws is checked on each falling edge of busclk after command is active. detection of -0ws low causes the command to end of the next rising edge of busclk. -0ws is operative in this manner on all cpu accesses to the at bus, including i/o as well as memory, 8-bit as well as 16-bit. it is not valid for iochrdy and -0ws both to be low during the same bus cycle. neither iochrdy nor -0ws is ever driven by the 82c836. these signals are 82c836 inputs only. figure 11-5. iochrdy and -0ws n cpu access to at-bus system timing relationships 11-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
-na/-stcyc timing figure 11-3 shown earlier identifies all possible timing relationships for the -na/-stcyc output from the 82c836. if -na mode has been selected (via the -dack3 strap option), the default state of -na during idle periods is low. -na is sampled by the cpu at the middle of t2 or t1p. if the 82c836 -na output is connected to the cpu -na input and -na is high during a bus cycle, the cpu will operate in nonpipelined mode during the cycle, and the cycle ends with a t2 state, not t2p. -na always goes low at the end of the final t2 of each cycle. it goes high again if needed as the start of the next t2 after t1. if -na stays low during a cycle, it will go high if needed at the start of the next ts (t1p or first t2 after t1). if the 82c836 -na output is not connected to the cpu -na input, then it is possible for the cpu to remain in pipelined mode even though the 82c836 -na output is high. in this case, -na still goes low at the end of the final t2p, but it may go high again at the middle of the following t1p. thus, there is a guaranteed low time of one procclk on the 82c836 -na output, which allows it to remain usable as an address latch enable signal (-adrl). if the -stcyc mode is selected instead of -na, then the cpu -na input must be tied high or low or controlled externally, and external latches (74f543 or equivalent) must be used between the cpu address bus and -sa bus. as shown in the diagram, -stcyc goes low during the first half of each ts, thereby signalling external devices that a bus cycle is starting. this timing also allows -stcyc to function as an address latch enable for the a0-23 to -sa bus latches. the -na/-stcyc output is forced low when hlda is high. this is redundant in the -na mode, since -na is low between cpu bus cycles in any case. in -stcyc mode, forcing -stcyc low causes the -sa bus address latches (if used) to become transparent while hlda is asserted, thereby allowing dma and refresh addresses to pass through (master addresses flow through in the opposite direction and are not latched by -adrl. in -na mode, the -na output operates as a ?? local memory hit ?? indicator. low on -na at mid-ts indicates that the 82c836 has detected a cpu read or write to local dram. in all other cases, -na is high at mid-ts. depending on cpu address delay and the exact address decoding path taken through the 82c836, it is possible for -na to glitch momentarily at the start of ts if -na was low during the preceeding bus cycle. as long as cpu address delay is within cpu specifications, -na will be stable and valid by the middle of ts, where the cpu samples it. the duty cycle of -ads provides a quick indication of whether or not the cpu is operating in pipeline mode. if -ads goes back low at any time during a bus cycle before the end of -ready, the cpu has entered the pipeline state (t2p) and the next t-state after ready will always be t1p, never t1 or th. on the other hand, if -ads is still high when -ready is asserted, the next t-state after ready will be t1, ti or th, but never t1p. if a bus cycle ends in a nonpipelined state (t2), the only way the cpu can get back into the pipeline state (t2p) is to go through t1 and at least one t2 first. -na/-stcyc operation and timing are unaffected by ?? cycle claiming ?? in the early ready or lba modes. the state of -na at mid-ts still indicates whether or not the 82c836 detected a cpu memory access at an address that resides in local dram. system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-9
-cas only dram access by cpu figure 11-6 shows the fastest possible cpu accesses to local dram. -ras and row address are already valid from a previous cycle, so only -cas needs to be cycled. the basic protocol is: column address becomes valid at start of ts. -cas goes low one procclk later (for read), four procclks for write. -cas stays low until end of cycle. read data becomes valid by end of cycle. write data and parity are valid at mid-ts. in pipeline mode, the shortest possible local memory read cycle is two t-states: t1p, t2p. the shortest possible pipelined memory write is t1p, t2p, t2p (three t-states). the extra t2p during writes allows time for parity generation. nonpipelined cycles follow the same timing except for an added t1 state at the beginning. the -cas active time is three procclk cycles for read, and two procclk cycles for write. the minimum -cas high (precharge) time is one cycle of procclk. minimum column address setup time before -cas goes active is one procclk. minimum column address hold time after -cas goes active is also one procclk. for external cache support, the end of the -cas pulse has a small additional propagation delay built-in so the read data will remain valid long enough for the cache data ram to capture it (cache read miss cycle). see the section titled early ready and lba modes for other cache related timing. -mwe is normally low so it can be used externally as a memory data buffer direction control if desired. a small extra -mwe delay is provided at the end of the -cas pulse to insure that -cas always goes inactive before -mwe goes back low. if the cycle is nonpipelined, the falling edge of -mwe is delayed until the middle of the next t-state. if the ?? -cas extend ?? wait state is enabled, one additional t-state is inserted in the -cas active time. if internal ems, early ready mode or lba is enabled (individually or in any combination), an extra t-state may be inserted at the beginning of the cycle before -cas goes active. the extra t-state allows time for ems address translation and/or cycle claiming by external logic such as a cache controller. in the case of early ready or lba, the early wait state occurs only on bus cycles that can be claimed by external logic, and only if the cycle is not externally claimed. in the case of internal ems, the early wait state occurs only if access is made to one of the four page windows and the window has been enabled for ems, i.e., only if an ems address translation actually needs to occur. ale and command are not generated on the at bus during local memory accesses by the cpu. the cpu status signals (m/-io, d/-c, w/-r) are latched internally at mid-ts. n cpu access to at-bus system timing relationships 11-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-6. -cas-only dram access by cpu system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-11
local dram bank switch (sra mode) figure 11-7 shows cpu accesses to local dram in zero wait state mode with -ras initially high. these timing relationships apply when the dram bank needs to be accessed is different from the bank for which -ras was already active. since -ras for the desired bank was already high, no further -ras precharge time is required for the desired bank. the basic protocol is the same as for cas-only cycles, except as follows: -ras for the target bank goes active at the middle of ts, and -ras for the previously active bank simultaneously goes inactive. row address is valid for one procclk before and after -ras goes active. if encoded ras is being used, -ras3 goes inactive at the middle of ts; one procclk later, ras0-2 change to the new value; after one more procclk, -ras3 again goes active. the net penalty for encoded ras is one t-state (only for bank switch cycles). these diagrams also apply if no -ras was previously active. this can happen during the first local memory access following a refresh or dma cycle, or following a ras timeout. the minimum bank switch cycle for nonencoded ras consists of t1p, t2p, t2p (three t-states). for encoded ras, an extra t2p is needed. for nonpipelined operation, an extra t1 occurs at the beginning of the cycle. as with cas-only cycles, a cas extend wait state can also be enabled. an early wait state can also be enabled for ems or external cache support. minimum -cas active time is two procclk cycles for write, or three procclk cycles for read. the minimum time allowed for read data access from -ras active is five procclk cycles. local dram ras high cycle (mra mode) in mra mode, bank-switch timing differs from sra mode as follows: ras for the new bank frequently is already low, and the row address previously latched by the drams is already valid. in that case, bank switch timing is exactly the same as page hit timing shown in figure 11-6. the fastest possible bank-switch read in mra mode is two t-states, while the fastest possible bank-switch write in mra mode is three t-states (cpu running in pipeline mode). if ras for the new bank is not already low, then the cycle follows the nonencoded ras timing shown in figure 11-7, except that ras for the previously accessed bank remains low instead of going high at mid-ts. mra mode, therefore, saves one t-state over sra mode for bank-switch (page-hit) dram reads. since the majority of dram accesses will be reads (mostly code fetches), and will be dram page-hits, the total reduction in t-states can be substantial. this the key performance advantage of mra mode over sra. n cpu access to at-bus system timing relationships 11-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-7. local dram bank switch system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-13
maximum wait state page miss figure 11-8 shows the fully-burdened local dram cycle i.e., the longest possible cycle (eight t-states). it is a page miss cycle, meaning the target bank is the same as the previously selected bank, but the row address must be changed. thus, the same -ras signal must be cycled high and then low again. state t1 occurs only if the cpu ended the previous cycle in nonpipeline mode. interval a is the early wait state, applicable only when internal ems, early ready or lba modes are enabled. intervals b and c are needed for -ras precharge time. for an encoded -ras bank switch, only b is needed. for -cas only cycles, neither b or c is needed. intervals d and e are the normal ras, row/column and cas sequence. only e is needed with cas-only cycles. interval f is the cas extend wait state (optional). with the early wait state enabled, the minimum -cas precharge time increases from one procclk cycle to three. with the cas extend wait state, the minimum -cas active time increases from two procclk cycles to four. neither type of wait states affect the delay from -ras to row address hold, or from column address valid to -cas active. ras timeout, if enabled, operates as follows: if -ras remains low long enough to cause a ras timeout (nominally 9.5 microseconds), the current memory cycle (if any) is allowed to finish, and then -ras is forced high at the middle of the next t-state after the end of the cycle. the -ras that had been active remains high for a minimum of four procclks. if an attempt is made to access the same bank again, the timing will follow either a page miss or a bank switch sequence as needed to insure four procclk cycles minimum high time on -ras. if access is made to a different bank, normal bank switch timing is followed. n cpu access to at-bus system timing relationships 11-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-8. maximum wait state page miss system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-15
cache mode write cycles figure 11-9 shows local dram write timing when early ready and/or lba mode is enabled. the diagram shows a page hit write (zero wait states) followed by a page miss write (three wait states). a ras high write (not shown) has the same timing as a page miss write except the ?? ras precharge ?? interval, two t-states in duration, is deleted, resulting in a one wait state cycle. in a ras high write, the falling edge of ras occurs at the middle of the first t2 instead of the middle of the third t2. there is a slight difference in cas timing between the 82c836b and the 82c836a. cas timing for the 82c836a is shown in dashed lines. 82c836b timing improves the write data hold delay after cas goes active. the ability to perform page hit writes in zero wait states provides a significant performance benefit in cache-based systems. since all writes go to dram (except in a diagnostic mode), streamlining write cycles to the same zero wait state performance as cache hit reads should result in a level of performance approaching buffered write-through or write-back cache architectures. actual performance depends on the number of dram banks, dram page size, and ratio of dram page hits to page misses on ras high cycles. zero wait state write timing is made possible by allowing cas to extend into the t1 state of the next cycle. this also relies on the fact that nonpipeline cpu mode must be used when early ready and lba modes are enabled in scatsx. if icr 63h bit zero is set to one, an early wait state is inserted after t1 to allow time for external logic to claim the cycle via early ready or lba. n cpu access to at-bus system timing relationships 11-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-9. cache mode write cycles system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-17
early ready and lba modes figure 11-10 shows how external logic can claim a cpu generated cycle by asserting -lba (0ws pin) or -ready during the first t2. in both cases, the 82c836 is prevented from generating a local memory or at bus cycle. for a read, the external logic (typically a local cache) must provide the read data and generate -ready. the 82c836 is responsive to early -ready or -lba only if one or both of these modes has been enabled by internal configuration register 41h. any cpu generated cycle, except a local memory write, can be claimed in this fashion, including interrupt acknowledge cycles. local memory writes normally cannot be claimed by external logic and do not cause an early wait state. however, even local memory writes can be claimed (and there will be an early wait state) if icr 63h bit 0 is set to one. when these cycle claiming capabilities are used, the cpu must run in nonpipelined mode only; the cpu -na input must be tied high. this is necessary because of cpu address timing. if the cycle is not claimed, then the 82c836 may need to generate a local memory cycle. the 82c836 needs a valid cpu address in order to do this, but in pipeline mode the cpu address may become invalid too soon for the 82c836. whenever the 82c836 finishes driving -ready during any cycle, it continues to drive -ready actively high for one procclk cycle. then -ready is tri-stated, and an external pull-up resistor keeps it high. the tri-stating of -ready cannot occur later than figure 11-10. early ready and -lba n cpu access to at-bus system timing relationships 11-18 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
mid-t1. since the earliest that the 82c836 could assert -ready again is during the third t2 after t1 (early wait state enabled), the first t2 after t1 is available for external logic to assert -ready without conflicting with the 82c836. the 82c836 samples -lba and -ready at the end of the first t2 after t1. -ready active at that time terminates the cycle. -lba active at that time causes the 82c836 to look for -ready at the end of each subsequent t2 state. the cycle terminates when the external logic asserts -ready. -lba is ignored and is ?? don?t care ?? at all times other than at the end of the first t2 after t1. if the external logic asserts both -lba and -ready at the end of the first t2 (not a valid combination), the cycle terminates just as if -ready alone had been asserted. the net performance effect of local cache is as follows: greatly increased percentage of two t-state memory reads due to high cache hit ratio (without cache, two t-state memory reads would still be possible in pipelined page mode, but the hit ratio would be considerably lower than with a cache). cache read misses increase from two t-state minimum to four t-states for -cas only memory reads. since cache read misses occur far less often with cache than without it, this penalty for cache read misses should have only a minor impact on overall system performance. page hit writes can occur in zero wait states, as compared to one wait state minimum in noncache modes. coprocessor timing figure 11-11 shows the relationship between the coprocessor busy and error signals and the busy signal sent to the cpu. normally, -busy to the cpu simply follows -npbusy from the coprocessor. when a coprocessor exception occurs (-nperr asserted), -busy to the cpu is latched (active) until the cpu acknowledges it by performing an i/o write to prot f0h. this protocol is at-compatible and differs from the ?? generic ?? coprocessor interface internal to the 80386sx cpu. in particular, the -error input to the cpu should be tied high, and at-compatible software will rely on interrupt level 13 for reporting coprocessor exceptions. the -nperr signal from the coprocessor is eventually cleared by i/o writes to the coprocessor sometime after the output to port f0h. figure 11-11. coprocessor timing system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-19
the 80387sx coprocessor monitors -ads, -ready, and cpu address bit 23 directly to detect i/o operations addressed to it. the coprocessor operates roughly as a 16-bit data resource except as follows: 1. in all cases, coprocessor data is exchanged on the cpu local data bus, not on the at bus. -iocs16 is not asserted. 2. if no coprocessor is present, attempted coprocessor i/o accesses result in bus convert cycles, including ale and command on the at bus, but the data bus drivers in the 82c836 remain tristated. this allows plenty of time for the floating cpu data bus to stablize to a valid state (a stable data bus is important for compatibility with certain older software products that rely on attempted coprocessor i/o operations to detect coprocessor presence or absence). 3. if a coprocessor is present, but the 82c836 has been programmed to generate -ready during coprocessor accesses, ale and command are generated. the cycle follows normal 16-bit i/o timing except as mentioned in (1) above. 4. if a coprocessor is present and the 82c836 has been programmed to rely on the coprocessor to generate -ready, ale and command are not generated, and the cycle ends as soon as the coprocessor issues -ready, which may be considerably sooner than in (3) above. zero wait state cycles are possible when the coprocessor generates -ready. since the coprocessor interface is tighly coupled to the cpu (rather than using an -xior/-xiow interface), the coprocessor is not accessible by add-on card bus masters. dma timing figure 11-12 shows a dma operation consisting of two back-to-back dma transfers between a memory resource and an i/o resource. the general protocol is as follows: a dma requestor asserts an assigned dreq signal. the 82c836 then asserts hold to the cpu. eventually the cpu responds with hlda, causing aen to be asserted on the at bus (externally gated with -master). hlda also causes ale to be asserted. ale remains continuously asserted until hold is subsequently deasserted. some time after detecting hlda, the 82c836 generates the dma memory address and issues the appripriate -dack signal, followed by either -xior and -xmemw, or xmemr- and -xiow. the address bus contains the memory address and is used by the memory resource. the i/o resource that should respond to the dma cycle is determined by the -dack signal. other i/o resources not involved in the dma cycle generally rely on aen to signify the address on the bus is not an i/o address. n cpu access to at-bus system timing relationships 11-20 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-12. dma timing system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-21
dma channels 0-3 are designed for 8-bit transfers involving 8-bit i/o resources. the memory resources can be either 8-bit or 16-bit. -iocs16 is ignored, but -memcs16 is used in conjunction with sa0 and -sbhe to control byte swapping between sd0-7 and sd8-15. address bits 0-15 increment or decrement by one after each dma cycle. software intervention is needed to change the contents of address bits 16-23. dma channels 5-7 are designed for 16-bit transfers involving 16-bit i/o resources. the memory resources must be 16-bit, also. -iocs16 and -memcs16 are ignored, and -bhe and a0 are both driven low. address bits 1-16 increment or decrement by one (i.e., address 0-16 increments or decrements by two, always even) after each dma cycle. software intervention is needed to change the contents of address bits 17-23. dma timing is driven by the internal dma clock, which is either the same as busclk or reduced to busclk/2 (programmable). figure 11-12, shown earlier, identifies hardware defaulting timing which is at-compatible. the default dma clock is busclk/2. timing is divided into s states, each consisting of one dma clock. the middle address bits (8-15 or 9-16) are updated at the middle of s1. low-order address bits (0-7 or 1-8) are incremented at the middle of each s2. -xior is asserted (if needed) at mid-s2, but -xmemr is asserted (if needed) at mid-s3. assertion of -xmemr can be changed to mid-s2 using icr 01h. -xiow and -xmemw are asserted as needed at mid-s3. this can be changed to mid-s2 using extended write mode. there is one dma wait state. sw (programmable up to four), and all commands are de-asserted at mid-s4. using compressed mode, the s3 states can be eliminated. s3 events, in that case, occur in s2 instead of s3. sw states are not affected. tc, if asserted, coincides with -xmemw or -xior. detection of iochrdy low at the end of sw causes additional sw states to be inserted until iochrdy is detected high at the end of an added sw. although iochrdy during dma is normally controlled only by memory resources, not i/o resources, the 82c836 has no means to distinguish the source of an iochrdy de-assertion and will respond in the same way regardless of which resource is controlling iochrdy. dreq is also sensed at the end of each sw. if dreq is detected low, the dma operation terminates after the end of the current dma cycle. dma and master access to local memory is shown in figure 11-13. n cpu access to at-bus system timing relationships 11-22 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-13. dma and master access to local memory system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-23
if -ras was active before hlda was asserted, -ras is forced high immediately (rising edge of hlda). additional memory timing during dma and master cycles is shown in figure 11-15. to meet cpu timing requirements, hold is synchronized to procclk. from the middle of the final s4 state to the falling edge of hold there is a minimum delay of two complete cycles of the 14.3mhz osc clock and an additional minimum delay of one complete cycle of procclk. the involvement of the 14.3mhz clock is for arbitration with refresh. s0 is entered after assertion of hold, s0 is then repeated as needed until hlda is detected. when hlda is detected high at mid-s0, s1 will be entered either immediately (dma channels 5-7) or after three more s0 states (channels 0-3). the additional s0 states for channels 0-3 occur because of the cascading between those channels and channels 5-7. if the dma clock is set to busclk rather than busclk/2, each s state is still one cycle of the dma clock, and, except for the frequency of the dma clock, s-state timing remains the same as described previously. drq/dack scanning in mra mode figure 11-14 shows how drq scanning and dack encoding are performed in multiple ras active (mra) mode. the seven drq signals are continuously scanned, two at a time, and latched inside the 82c836. one pair of drq signals is scanned every 70ns (based on the 14.3mhz clock source) using an external 74f153 multiplexer. if the 82c836 internal 8237a-compatible logic decides to recognize one of the internally latched drq signals, scanning stops and locks onto the corresponding drq signal. at about the same time, the dack signal issued by the internal 8237a-compatible logic is encoded and generated on the dacka-c lines. finally, -dacken goes active (low), enabling the external 74als138 decoder to reconstruct the appropriate dack output. the scanning mechanism remains frozen on the selected drq signal until the dma transfer is completed and the corresponding dack signal is deasserted. usually this will occur in response to external logic deasserting the drq signal. scanning then resumes from the lock-in point and continues until the next drq signal is recognized by the internal 8237a-compatible logic. it is possible for more than one drq signal to have been scanned and latched inside the 82c836 before the internal 8237a-compatible logic decides to recognize one of the internally latched drqs. in fact, if a dma channel has not been enabled by software, a latched drq for the disabled dma channel will never be recognized by the 8237a-compatible until software enables the channel logic. meanwhile, other dma channels are free to function normally as programmed by the software. figure 11-14 illustrates the drq scanning process followed by recognition of drq0 or drq5. only four cycles of the 14.3 mhz clock are needed to completely scan and internally latch all seven drq signals. n cpu access to at-bus system timing relationships 11-24 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-14. drq/dack scanning in mra mode system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-25
master arbitration figure 11-15 shows how an add-on card bus master obtains, and later releases, control of the buses. the general at-compatible protocol is as follows: the master asserts an assigned dreq and waits for the corresponding -dack, just as in a dma sequence. however, before a dma channel can be used for master operation, software must program the channel for cascade mode. then, when dreq is received for that channel, the 82c836 refrains from starting a dma cycle after issuing -dack. upon receiving -dack, the requesting master asserts the master signal. this reverses the directions of various bus drivers, forces aen to be de-asserted, and signifies that the master is now in control. the master can remain in control indefinitely, performing i/o or memory reads and writes as needed. the master releases control by deasserting -master and dreq. master read and write cycles on the at bus follow the same basic protocol as cpu reads and writes to the at bus, except as follows: address and command are controlled by the add-on card bus master and are not necessarily synchronized to busclk. ale remains continuously high, and timing for ua17-23 is the same as the timing for sa0-19. data transfer is between the master and an i/o resource, or between the master and a memory resource, using the same command signals as cpu controlled cycles. figure 11-15. master arbitration n cpu access to at-bus system timing relationships 11-26 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
byte swapping remains the responsibility of the 82c836, but any bus conversion that might be needed must be performed by the add-on card bus master. for byte swapping purposes, the master is treated as a 16-bit resource and must not drive the sd0-7 and sd8-15 buses in a way that would conflict with byte swapping being performed by the 82c836. -smemr and -smemw remain under control of -lomegcs, which is driven by the 82c836 in response to the at bus address generated by the master. while an add-on card bus master is in control, it can request a refresh cycle by driving the -refresh signal low. the 82c836 will then perform a refresh cycle in the normal manner, controlled by the 82c836. by holding -refresh low longer than needed for a single refresh, the master can request multiple back-to-back refresh cycles. dma and master access to local memory during dma and master cycles, (see figure 11-13) local memory timing follows a somewhat different protocol than during cpu cycles: if any -ras signal was low, it is driven high when hlda goes high. a0-23 flow through the 82c836 to determine the row address. the 82c836 then waits for -xmemr or -xmemw to be asserted. the memory command causes -ras to go low immediately. two rising edges of procclk must then occur (a, b) before row/column changeover takes place. one procclk after that, -cas is asserted (c). on master writes, additional clock cycles can be programmed between b and c (see icr 64h). -cas, -ras and column address remain valid until the end of command. if the cycle is a memory read, -mwe is driven high at the same time that -ras is driven low. memory refresh (hlda and 14mhz-based) figure 11-16 shows cas-before-ras using hold/hlda protocol and the 14.3mhz time base. it applies to either system initiated refresh or master initiated refresh while power is good (pwrgood high). refreshing ceases during power down unless standby refresh has been enabled (see icr 60h). laptop applications using the 82c836 can use standby refresh to preserve dram contents during power down. the basic 82c836 refresh protocol is as follows: if a system initiated refresh immediately follows a dram write in early ready or lba mode (as depicted in figure 11-16), cas goes high at the middle of the first th, and ras goes high at the end of the first th. in all other cases of system initiated refresh, hlda causes all ras lines to go high. system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-27
two procclk cycles later, -refresh is asserted. for master intitated refresh, the add-on card bus master asserts -refresh. ale follows hlda and hold as in dma cycles. -lomegcs follows -refresh. refresh address, -xmemr and -ras are synchronized to the 14.3mhz clock. the width of -xmemr is programmable (see icr 41h). for at-compatibility, the width should be set to four clocks (280ns). the width of -xmemr can also be extended, one 14.3mhz clock cycle at a time, by driving iochrdy low. -mwe is the inverse of -cas; it goes high while -cas is low. the delay from hlda rise to -ref fall during cas-before-ras refresh allows for cas precharge time. the worst-case for cas precharge is when a zero wait state cache-mode write is immediately followed by a refresh cycle. cas can extend past the end of -ready by up to one full procclk cycle in that case, as shown in figure 11-16 (see also figure 11-9). when using nonencoded ras, -ras1 and -ras2 are delayed slightly relative to -ras0 and -ras3 during refresh. this staggered refresh is intended to reduce the net instantaneous dram power surge resulting from -ras assertion. a0-10 contain the refresh address, incremented at the end of -ref (rising edge). a16-23 contain the refresh page register value, normally zero (programmable). a11-15 are undefined. the dram uses its own internal refresh address counter during cas-before-ras refresh, but the refresh address generated by the 82c836 is still needed on the at bus. as in dma cycles, hold is synchronized to procclk. the falling edge always occurs at the start of t-state. when using ras-only refresh instead of cas-before-ras refresh (see icr 60h), refresh timing differs from the foregoing as follows: -cas remains high during ras-only refresh. -mwe remains low during ras-only refresh. the two procclk delay between -ras rise and -ref fall is deleted; -ref goes low on the same procclk edge on which -ras goes high. the drams rely on the 82c836 to provide the refresh address during ras-only refresh. n cpu access to at-bus system timing relationships 11-28 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-16. refresh timing (hlda/14mhz-based) system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-29
hidden refresh (procclk-based, no hlda) figure 11-17 shows hidden refresh timing. in hidden refresh, the cpu is allowed to continue operating during refresh cycles. hold and hlda are not used. obviously, the cpu cannot be allowed to access local memory or the at bus during refresh. so, the main usefulness of hidden refresh is in cache based systems to allow cache read hits to continue during refresh. the basic protocol for hidden refresh is as follows: if a cpu cycle is already in progress when the 82c836 needs to perform a refresh cycle, the 82c836 waits for the cpu cycle to end (indicated by -ready). if no cpu cycle is in progress (-ready has occurred but no new -ads yet), the hidden refresh cycle can begin immediately. the 82c836b asserts ale throughout the hidden refresh cycle. two procclk cycles after ale goes high, -ref and -lomegcs go low. -cas goes low on the same procclk edge as -ref. the delay from ale to -ref allows time for cas precharge when using cas-before-ras refresh. after additional delay, -xmemr and -ras go low for a few procclks, then back high. the 82c836 provides the refresh address for the drams using ma0-10, but other external logic must provide the refresh address for the at bus. as in hlda based cas-before-ras refresh cycles, -mwe goes high while -cas is low. a few procclks after the end of -xmemr, -ref goes high. finally, after further delay, ale goes low. if the cpu attempted to start a local memory or at bus access during the hidden refresh cycle, cpu wait states are inserted as needed to allow the refresh to complete. when ale goes low, the waiting cpu cycle is allowed to proceed. the t1 state for the waiting cpu can overlap the hidden refresh cycle, but the normal t2 states begin after ale goes low. for example, figure 11-17 shows a local memory write being delayed until the end of the hidden refresh. -ras goes low for the memory write in the middle of the first t-state after the end of the hidden refresh. since hidden refresh is useful only in cache-based systems, which must use nonpipeline mode, hidden refresh is designed to work in nonpipeline mode only. -mwe needs to go high during cas-before-ras refresh to prevent the drams from going into test mode. this is incompatible with the use of md buffers if -mwe is used as the direction control for the buffers; a high logic level on -mwe would cause the md buffers to drive the cpu local data bus, interfering with cache read hit activity. thus, in a cache-based system using hidden refresh, md buffers should not be used. worst case system timing and loading analysis shows that md buffers aren?t needed in any case, in any cache or non-cache configuration; worst-case system timing margins are better without md buffers. n cpu access to at-bus system timing relationships 11-30 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
figure 11-17. hidden refresh (procclk-based, no hlda) system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-31
the following programmable options are available with hidden refresh (icr 63h): ras-only refresh ---- in ras-only refresh, -cas remains high and -mwe remains low. at refresh off ---- in this mode, ale, -ref and -xmemr remain inactive during hidden refresh. iochrdy has no effect. only the local dram is refreshed, not the at bus, and the total refresh cycle time is correspondingly shorter (see table 11-1). for compatibility with many at bus add-in cards, at refresh should not be turned off. refresh on idle ---- enabling this option prevents hidden refresh from starting until after a cpu idle state. normally, a hidden refresh can begin as early as the next t-state following -ready, as shown in figure 11-17. refresh on idle prevents a hidden refresh from starting if the next t-state after -ready is a t1-state (-ads asserted). in most systems, refresh on idle will probably have no measurable performance effect and should remain disabled. the exact number of procclk cycles between various events in hidden refresh depends on the cpu speed as programmed in icr 63h. the procclk counts also depend on whether at refresh is enabled or disabled, as in the following table. table 11-2. procclk cycles and hidden refresh events 16mhz 20mhz 25mhz ale rise to -ref/-cas fall 2 2 ? 2 2 ? 2 2 ? -ref/-cas fall to -xmemr/-ras fall 4 1 ? 5 2 ? 7 2 ? -xmemr/-ras fall to iochrdy sampling 2 ---- 3 ---- 4 ---- iochrdy sampled high to -xmemr/-ras rise 5 ---- 6 ---- 7 ---- total -xmemr/-ras low time without iochrdy 7 4 ? 9 4 ? 11 4 ? -xmemr/-ras rise to -ref/-cas rise 2 1 ? 3 1 ? 3 1 ? -ref/-cas rise to ale fall 4 ? 4 ? 4 ? 5 ? 4? 5 ? total hidden refresh time without iochrdy 20 12 ? 24 14 ? 28 14 ? ? denotes at refresh off. ? plus one procclk if needed to make ale fall at end of t-state. standby refresh (32khz-based) in addition to hlda refresh (14.3mhz based, cas-before-ras or ras-only) and hidden refresh, the 82c836b also supports standby refresh (useful only in cas-before-ras mode). standby refresh operates only if it has been enabled via icr 60h. it allows the contents of dram to be preserved during power down. figure 11-18 shows standby refresh timing: pwrgood going low indicates the imminent loss of main power. the 82c836 may complete one more normal refresh (hlda or hidden), but must then switch to standby refresh as quickly as possible. n cpu access to at-bus system timing relationships 11-32 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
each standby refresh cycle starts with -cas going low and -mwe going high. after a short delay, -ras goes low. after a further delay, -ras goes back high. after more delay, -cas goes high and -mwe goes low. figure 11-18. standby refresh (32khz-based) system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-33
the various time delays during standby refresh are generated via asynchronous gate delays. standby refresh is based on the 32khz time base. the 32khz clock should be designed to operate on battery power (along with the 82c836) when main power has been turned off. each edge of the 32khz clock triggers a cas-before-ras refresh cycle. the drams, of course, must also operate on battery power in order to preserve their contents during main power interruptions. there should be either no buffering of -ras, -cas, and -mwe to the drams, or battery backed buffers should be used. as shown in figure 11-18, the transition from normal refresh to standby refresh occurs automatically in response to pwrgood going low. the transition back to normal refresh after pwrgood goes back high is somewhat more complicated. first, bios must restart normal refresh by appropriately programming the 14.3mhz based refresh timer. after the refresh timer starts running again, 32khz based refresh is stopped and 14.3mhz based refresh starts up. for laptop applications, both normal refresh and standby refresh should use cas-before-ras protocol in which the drams generate their own refresh addresses internally. power turn-on and system reset figure 11-19 shows what happens immediately following power turn-on. except for vcc and ps, this sequence applies to the cycling of pwrgood by means of a hardware reset switch as well as power turn-on. figure 11-19. power-on n cpu access to at-bus system timing relationships 11-34 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
vcc typically ramps up very slowly (perhaps 100ms or more) relative to the high speed of the 82c836 and cpu. at around 2 or 3vdc, logic that wasn?t already functioning on battery power begins operating, but pwrgood from the power supply remains low. pwrgood typically stays low until several hundred microseconds after vcc reaches its valid operational value (4.75vdc minimum). while pwrgood is still low: all outputs except the 14.3mhz driver are held in the high impedance state. in particular, xrst and cpurst are floating and should be externally pulled up. procclk and busclk also float. the 14.3mhz driver is held at a continuous low level. it does not float. the -dack lines should be pulled up or down depending on the desired strap options. -nperr should be pulled up, but will be driven low if a coprocessor is present. eventually, pwrgood goes high. at this point, procclk and busclk start running and the 14.3mhz oscillator is allowed to start running. there will typcially be a significant start-up time for the 14.3mhz oscillator, potentially 1000 microseconds or longer. an internal 1.19mhz clock (14.3mhz divided by 12) starts running when the 14.3mhz clock starts up. the -dack lines (strap options) are sampled and latched approximately 128 cycles of 1.19mhz after the 14.3mhz oscillator starts running. after an additional 128 cycles of 1.19mhz, -nperr is sampled and xrst and cpurst go low. the sampling of -nperr is automatic coprocessor-present detection. there is, therefore, an interval of approximately 200 microseconds during which all clocks are running and both resets are still high. allowing busclk and 14.3mhz to run during reset has been found to be necessary for reliably resetting the 8042/8742 keyboard controller and certain add-on cards on the at bus. cpurst can occur alone, without xrst (see the section titled cpu access to at bus ). the pulse width of cpurst in such cases is 22 cycles of procclk, and the falling edge occurs at the middle of a t-state. there is no mechanism for synchronizing the 82c836 internal phase clock to any external source; rather, all phase clocks outside the 82c836 must be synchronized to the 82c836 via cpurst or xrst. the foregoing operation is changed as follows when standby mode is enabled: if power sense (mfp5) is low at any time while pwrgood is low, standby mode is cleared and the system reacts to pwrgood exactly as described above. when using standby mode, the 82c836 and ps (mfp5) signal must remain powered up even when pwrgood is low. in normal system operation, a battery will do this. in a test environment with no battery connected, standby mode can be tested by driving pwrgood low without actually turning power off. when pwrgood goes low while standby mode is enabled, the 82c836 attempts to switch to standby refresh (32khz based). pwrgood is internally blocked from having any further effect until the switch to 32 khz based standby refresh is successful. to prevent disruption of memory refresh, at least one additional normal refresh must occur before the 82c836 switches to standby refresh. there is a 32 khz based timeout to prevent a possible system lockup if normal refresh has stopped running for any reason (such as erroneous programming by the software). if the timeout elapses before the switch to standby refresh occurs, indicating that there is system timing relationships cpu access to at-bus n chips and technologies, inc. p r e l i m i n a r y revision 3.0 11-35
a major malfunction in memory refresh, then the standby mode is cleared completely and the system recovers as if standby mode had not been enabled. the timeout interval is approximately 15 refresh periods at the currently programmed standby refresh rate (icr 60h, bits 4 and 5). since refresh requires the use of -ras, -cas, ma, and -mwe signals, these signals remain active during standby refresh instead of being tristated. (the ma lines are driven to a continuous logic high level. no refresh address is generated; rather, cas-before-ras refresh must be used along with standby refresh.) the icr bits for memory configuration and mra enable are also preserved during power down if standby mode is enabled. see the section titled standby power management and laptop support for more precise definition of which outputs remain actively driven during power-down standby mode. since dack signals become cas lines during mra mode, dack sampling during xrst (see figure 11-19) is suspended when powering back up from standby mode. the previously sampled state of the dack lines at the time of initial power application (before standby mode was enabled) is preserved. (the 82c836b has an internal hardware interlock to prevent standby mode from becoming or remaining enabled when external rtc is enabled. this interlock is necessary because the 32khz input is cut off when external rtc is enabled. without 32khz, standby mode cannot function and the system could lock up if standby mode is enabled.) in a manufactuirng or test environment, it often happens that the system is powered up initially with no battery connected. to keep the external ps (mfp5) circuit as simple as possible, the 82c836b automatically ignores the ps input when pwrgood is high. as soon as pwrgood goes high, the 82c836b operates as if ps were high even if ps is actually still low. (the 82c836a lacks this feature and requires ps to be high before xrst goes low. in addition, the 82c836a will malfunction if ps goes low at any time while pwrgood is high and xrst is low.) in a normal operating environment, a battery will have been connected before turning on the main power supply. in that case, ps (mfp5) will already be high before pwrgood goes high, and ps will remain high during subsequent power-down periods. for the 82c836b, the external ps (mfp5) circuit only needs to insure a brief interval (100ns should be adequate) of low time on ps (mfp5) after vcc to the 82c836 has reached 3.0v (see figure 3-3). n cpu access to at-bus system timing relationships 11-36 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
section 12 system characteristics physical characteristics tables 12-1 through 12-3 lists the physical characteristics of the 82c836 chipset. table 12-1. absolute maximum ratings symbol parameter min. max. units v cc supply voltage ---- 7.0 v v i input voltage -0.5 5.5 v v o output voltage -0.5 5.5 v t op operating temperature -25 85 c t stg storage temperature -40 125 c permanent device damage may occur if absolute maximum ratings are exceeded. functional operation sh ould be restricted to the conditions described under operating conditions. table 12-2. operating conditions symbol parameter min. max. units conditions v cc supply voltage 4.75 5.25 v operating v cc supply voltage 3.0 5.25 v standby t a ambient temperature 0 70 c table 12-3. capacitive characteristics symbol parameter min. max. units conditions c in input capacitance ---- 10 pf fc = 1mhz c i/o i/o capacitance ---- 20 pf unmeasured pins grounded c out output capacitance ---- 20 pf unmeasured pins grounded chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-1
dc characteristics table 12-4 summarizes the dc characteristics of the 82c836 chipset. table 12-4. dc characteristics symbol parameter min. max. units conditions v il input low voltage ---- 0.8 v ---- v ih input high voltage 2.0 v ---- v ol output low voltage drive for pins: -mwe, -xior, -xiow, -xmemr, -xmemw,ale, -refresh, procclk ---- 0.4 v i ol = 8ma v ol output low voltage drive for pins: a0-23, moda0, moda20, ma0-9, ras0-3, -cash, -casl, parh, parl, busclk, d0-15, xd0-15, -dackn, -iocs16, -memcs16, -na, -bhe, -ready, xrst ---- 0.4 v i ol = 4ma v ol drive for all other pins ---- 0.4 v i ol = 2ma v oh output high voltage drive for pins: -mwe, -xior, -xiow, -xmemr, -xmemw, ale, -refresh, procclk 2.4 ---- v i oh = -8ma v oh output high voltage drive for pins: a0-23, moda0, moda20, ma0-9, ras0-3, -cash, -casl, parh, parl, busclk, d0-15, xd0-15, -dackn, -iocs16, -memcs16, -na, -bhe, -ready, xrst 2.4 ---- v ioh = 4ma v oh drive for all other pins 2.4 ---- v ioh = -2ma v cl procclk output low ---- 0.4 v i ol = 4.0 ma v ch procclk output high ---- v cc -0.8 v i oh = -4.0 ma i il input leakage current -10 20 m a v i = 0 to v cc i ol output leakage current -10 20 m a v o = 0.45v to v cc i cc v cc supply current ---- 140 ma c xin = 50 mhz i ccsb v cc standby supply current ---- 50 m a pwrgood low, standby refresh is disabled n dc characteristics system characteristics 12-2 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
ac characteristics 16- and 20mhz all timing parameters are specified under capactive load of 50pf, vcc 4.75v to 5.25v, and temperature of 0 to 70 c, and allow operation at 16mhz with 100ns dram or 20mhz with 80ns dram without a cas-extended wait state. all the units discussed are in nanoseconds and are subject to change. unless otherwise noted, the following configuration options are also supported: memory configurations up to 8 banks using encoded ras (sra mode) memory configurations up to 4 banks using either sra or mra mode, nonencoded ras cache or non-cache nonlatching buffer between sa-bus and cpu local address bus formula specifications refer to the minimum or maximum result of a specified calculation involving other chip parameters. for any particular chip, formula specifications express a tracking relationship over temperature and voltage for the parameters involved in the formula. note that timing parameters are grouped into subsections according to the most common modes and cycle types to which they apply, but parameters are not necessarily limited only to those cases. unless otherwise noted, all min/max timing limits are valid for all modes and cycle types in which the referenced signals follow the stated functional relationship. the following terminology is used in the parameter descriptions: command = -xior, -xiow, -xmemr or -xmemw rise = low-to-high transition fall = high-to-low transition float = transition to high-impedance state turn-on = a signal coming out of ?? float ?? and driven high or low active = high for high-true signals, or low for low-true inactive = high for low-true signals, or low for high-true to assure reliable local memory operation under worst-case conditions, the drams should meet the specifications shown in the following table. most drams utilizing cmos technology can readily meet these specifications. system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-3
table 12-5. dram parameter specifications 16mhz 20mhz parameter min. max. min. max. read data valid from ras active (trac) ---- 100 ---- 80 read data valid from cas active (tcac) ---- 35 ---- 25 read data valid from column address (taa) ---- 55 ---- 45 cas active time (tcas) 35 ---- 25 ---- cas precharge time in page mode (tcp) 15 ---- 15 ---- cas cycle time in page mode (tpc) 85 ---- 70 ---- cas fall to ras rise (trsh) 40 ---- 25 ---- cpu to local memory tables 12-6 through 12-8 summarizes cpu to memory specification requirements. table 12-6. cpu to local memory ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t100 ras active from procclk rise ---- 33 ---- 23 t101 ras inactive from procclk rise ---- 33 ---- 32 t102 cas active from procclk rise ---- 23 ---- 23 t103 cas inactive from procclk rise ---- 28 ---- 27 t104 row address valid from procclk rise ---- 40 ---- 32 t105 row address hold from procclk rise 0 ---- 0 ---- t106 row address valid from a0-23 in ---- 50 ---- 50 t107 column address valid from procclk rise ---- 19 ---- 19 t108 column address hold from procclk rise 0 ---- 0 ---- t109 column address valid from a0-23 in ---- 50 ---- 47 t110 -mwe fall from -cas rise 0 60 0 48* t111 -mwe rise from procclk rise ---- 33 ---- 32 t112 parl, parh valid from d0-15 write data in ---- 55 ---- 55 t113 -ready delay from procclk rise 4 40 4 38 * 60ns maximum for 82c836a-20. n ac characteristics 16- and 20mhz system characteristics 12-4 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-7. cpu to local memory ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te101 ras precharge t101-t100 ---- 39 ---- 19 te102 ras-to-cas delay t100-t102 ---- 24 ---- 15 te103 cas precharge t103-t102 ---- 16 ---- 10 te103a cas rise to ras fall t103-t100 ---- 7 ---- 6 te104 row address setup before ras t104-t100 ---- 20 ---- 14 te105 row address hold after ras t100-t105 ---- 7 ---- 5 te106 row address setup before ras t106-t100 ---- 46 ---- 34 te107 column address setup before cas t107-t102 ---- 17 ---- 11 te108 column address hold after cas t102-t108 ---- 8 ---- 2 te109 column address setup before cas t109-t102 ---- 43 ---- 31 te111 mwe rise before cas fall t111-t102 ---- 16 ---- 10* te112 write parity setup before cas t112-t102 ---- 10 ---- 10 * 14ns maximum for 82c836a-20. table 12-8. cpu to local memory ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t120 parl, parh setup before procclk rise during read 9 ---- 9 ---- t121 parl, parh hold after procclk rise during read 6 ---- 6 ---- t122 d0-15 setup before procclk rise during read 9 ---- 9 ---- t123 d0-15 hold after procclk rise during read 6 ---- 6 ---- system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-5
cpu access to at-bus, on-board i/o, and rom tables 12-9 through 12-11 are the specification requirements for the cpu to access the at-bus, the on-board i/o, and rom. table 12-9. cpu to at-bus, on-board i/o, and rom ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t130 lomegcs delay from procclk rise ---- 40 ---- 35 t131 -na delay from procclk rise ---- 25 ---- 20 t132 -ready delay from procclk rise 4 40 4 31 t133 ale rise from busclk low ---- 25 ---- 25 t134 ale fall from busclk high ---- 20 ---- 15 t135 command and -romcs active from busclk ---- 30 ---- 30 t136 command and -romcs inactive from busclk rise ---- 25 ---- 25 t137 moda0 delay from procclk rise ---- 35 ---- 30 t138 moda0 rise from busclk fall during bus convert ---- 25 ---- 20 t139 moda20 delay from a20 if moda20 enabled ---- 35 ---- 35 t140 moda20 delay from hold fall ---- 59 ---- 50 t141 sdirl, h delay from procclk rise ---- 55 ---- 50 t142 xd0-15 delay from procclk rise during write ---- 55 ---- 50 t143 xd0-15 turn-on delay from procclk rise 5 ---- 5 ---- t144 xd0-15 turn-off delay from procclk rise ---- 55 ---- 50 t145 xd0-15 delay from d0-15 during cpu write or dma/master read ---- 30 ---- 30 t146 xd0-7 delay from d8-15 during cpu write or dma ---- 70 ---- 70 t147 d0-15 delay from xd0-15 during cpu read or dma/master write ---- 25 ---- 25 t148 d8-15 delay from xd0-7 during cpu read or dma ---- 45 ---- 40 n ac characteristics 16- and 20mhz system characteristics 12-6 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-10. cpu to at-bus, on-board i/o, and rom ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te133 ale width t133-t134 ---- 10 ---- 10 te137 moda0 hold after command rise t136-t137 ---- 16 ---- 16 te139 memcs16 setup before ale fall t139-t134 ---- 24** ---- 15** te145 master read, access from cas t145+t102 ---- 38* ---- 38* te145a master read, access from column address t145+t107 ---- 34 ---- 34 * 36ns maximum for 82c836a. ** 20ns maximum for 82c836a-20. 29ns maximum for 836a-16. table 12-11. cpu to at-bus, on-board i/o, and rom ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t160 -ads setup before procclk rise* 24 ---- 24 ---- t161 -ads hold after procclk rise* 4 ---- 4 ---- t162 a0-23 setup before procclk rise ? 57 ---- 45 ---- t163 a0-23 hold after procclk rise ? 4 ---- 4 ---- t164 -bhe setup before procclk rise ? 39 ---- 39 ---- t165 -bhe hold after procclk rise ? 4 ---- 4 ---- t166 -dc, w/-r and m/-io setup before procclk rise ? 39 ---- 39 ---- t167 -dc, w/-r and m/-io hold after procclk rise ? 4 ---- 4 ---- t168 iochrdy setup before busclk rise + 20 ---- 15 ---- t169 iochrdy hold after busclk rise + 20 ---- 15 ---- t170 0ws setup before busclk fall + 15 ---- 10 ---- t171 0ws hold after busclk fall + 25 ---- 20 ---- t173 -iocs16 hold after command inactive 0 ---- 0 ---- t174 -memcs16 setup before ale fall 33** ---- 30** ---- t175 -memcs16 hold after ale fall 10 ---- 10 ---- t176 xd0-15 valid before read command rise 25 ---- 20 ---- t177 -iocs16 setup before busclk rise (first busclk rise after i/o command fall) 0 ---- 0 ---- + certain input parameters, as noted, are nonrestrictive. if these parameters are violated, the sign al may not be recognized until the subsequent clocking period. the parameter specifies only the condition needed to guarante e recognition of the signal on the particular clock edge. ? at end of ts (ts is the t-state in which -ads changes from low to high). ? at mid-ts. * at start of ts. ** 28ns maximum for 82c836a at 16mhz. 25ns maximum for 82c836a at 20mhz. system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-7
dma access to at-bus, on-board i/o, and rom tables 12-12 through 12-14 are the specification requirements for dma to access the at-bus, on-board i/o, and rom. table 12-12. dma to at-bus, on-board i/o, and rom ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t190 -dackn or -dacken delay from busclk rise ---- 50 ---- 50 t191 ale rise from hlda rise ---- 75 ---- 70 t192 dma address delay from busclk rise ---- 40 ---- 35 t194 command fall from busclk rise ---- 45 ---- 40 t195 command rise from busclk rise ---- 45 ---- 40 t197 tc rise from busclk rise ---- 40 ---- 40 t198 tc fall from busclk rise ---- 40 ---- 35 t199 lomegcs delay from a16-23 ---- 35 ---- 35 t200 hold delay from procclk rise at start of t-state 5 36 5 33 t201 dsela, b delay from osc2 rise in mra mode ---- 35 ---- 35 t202 dacka, b, c valid before dacken fall in mra mode 0 ---- 0 ---- t203 dacka, b, c hold after dacken rise in mra mode 0 ---- 0 ---- note: dma address refers to a0-23, moda0, moda20, and -bhe. table 12-13. dma to at-bus, on-board i/o, and rom ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te194 command low time t194-t195 ---- 10 ---- 10 te195 command high time t195-t194 ---- 10 ---- 10 n ac characteristics 16- and 20mhz system characteristics 12-8 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-14. dma to at-bus, on-board i/o, and rom ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t210 hlda setup before busclk rise ? 20 ---- 15 ---- t212 dreq setup before busclk rise ? 20 ---- 15 ---- t213 dreq hold after busclk rise ? 20 ---- 15 ---- t214 iochrdy setup before busclk rise ? 15 ---- 10 ---- t215 iochrdy hold after busclk rise ? 7 ---- 5 ---- ? certain input parameters, as noted, are nonrestrictive. the signal may not be recognized until the subsequent clocking period if these parameters are violated. the parameter specifies only the condition needed to guara ntee recognition of the signal on a particular clock edge. dma and at-bus master access to local memory tables 12-15 through 12-17 are the specification requirements for the dma and the at bus master to access local memory. note: for xd, d, and par timing, use t145-t148 and t112. for row/column change over and cas active, use t102, t105, and t107. table 12-15. dma and at-bus master access to local memory ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t230 -ras high from hlda rise ---- 60 ---- 60 t231 a0-23 and -bhe float from -master active ---- 60 ---- 60 t232 command float from -master active ---- 35 ---- 30 t233 -mwe rise from -xmemr fall ---- 45 ---- 40 t234 -mwe fall from -cas rise 2 60 2 60 t235 -ras inactive from -xmemr or -xmemw high ---- 45 ---- 42 t236 -cas inactive from -xmemr or -xmemw high ---- 55 ---- 50 t239 -ras active from xmemr or xmemw ---- 36 ---- 36 t240 a20 valid from moda20 during master access ---- 25 ---- 25 t241 a0 valid from moda0 during master access ---- 24 ---- 24 t242 sdirl, h fall from -xmemw fall during master write ---- 40 ---- 40 system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-9
table 12-16. dma and at-bus master access to local memory ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te230 ras precharge before refresh t230-t263-t265 ---- 27 ---- 27 te233 mwe rise before cas fall (read) t233-t102 ---- 35 ---- 24 te235 ras precharge, master t235-t239 ---- 16 ---- 16 te239 master read, access from ras t239+t145 ---- 51 ---- 51 te240 row address to ras t240-t239+t106 ---- 25 ---- 25 te242 master write, sdir fall t242+t147 ---- 65 ---- 65 table 12-17. dma and at-bus master access to local memory ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t250 parl, parh setup before -xmemr rise during mem read 20 ---- 20 ---- t251 parl, parh hold after -xmemr rise during mem read 0 ---- 0 ---- refresh the refresh timing specifications and requirements are shown in tables 12-18 through 12-20. table 12-18. refresh ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t260 -refresh active from hlda ---- 71 ---- 71 t261 -refresh float from osc2 rise ---- 55 ---- 55 t262 refresh address valid from -refresh active ? ---- 45** ---- 45** t263 -xmemr active from osc2 rise ---- 60 ---- 55 t264 -xmemr inactive from osc2 rise ---- 55 ---- 50 t265 -ras0, -ras3 active from -xmemr fall ---- 35 ---- 30 t266 -ras0, -ras3 inactive from -xmemr rise ---- 30 ---- 25 t267 -ras1, -ras2 active from -xmemr fall ---- 75 ---- 70 t268 -ras1, -ras2 inactive from -xmemr rise ---- 75 ---- 70 ? refresh address refers to moda0, a0-9, and ma0-9. ** 40ns maximum for 836a. n ac characteristics 16- and 20mhz system characteristics 12-10 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-18. refresh ---- output responses (continued) 16mhz 20mhz symbol parameters min. max. min. max. t269 lomegcs delay from -refresh ---- 44 ---- 44 t270 -cas fall from hlda rise in cas-ras hlda refresh * ---- * ---- t271 -refresh active from procclk in hidden refresh, or in hlda refresh in early ready mode following memory write ---- 50 ---- 50 t272 -xmemr fall from procclk in hidden refresh ---- 50 ---- 50 t273 -xmemr rise from procclk in hidden refresh ---- 50 ---- 50 * not applicable to 82c836b. 10ns minimum for 82c836a. table 12-19. refresh ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te260 ref to xmemr delay in hlda refresh t260-t263 ---- 16 ---- 16 te270 cas precharge in cas-ras refresh t270-t103 * ---- * ---- te271 ref to xmemr in early ready mode t271-t263 ---- 16 ---- 16 te271a ref to xmemr delay in hidden refresh t271-t272 ---- 5** ---- 5** te272 xmemr low time in hidden refresh t272-t273 ---- 15*** ---- 15*** te273 address hold after xmemr rise t273-t271 ---- 50 ---- 38 * not applicable to 82c836b. 9ns minimum for 82c836a. ** 1ns maximum for 82c836a. *** 4ns maximum for 836a. table 12-20. refresh ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t280 iochrdy setup before osc2 rise ? 20 ---- 15 ---- t281 iochrdy hold after osc2 rise ? 7 ---- 5 ---- t282 -refresh setup before osc2 rise ? 25 ---- 20 ---- ? certain input parameters, as noted, are nonrestrictive. if these parameters are violated, the signa l may not be recognized until the subsequent clocking period. the parameter specifies only the conditions needed to guarant ee recognition of the signal on a particular clock edge. system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-11
miscellaneous parameters miscellaneous timing specifications are shown in tables 12-21 through 12-23. table 12-21. miscellaneous parameters ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t290 xrst inactive from procclk rise 4 18 4 13 t291 cpurst inactive from procclk rise 4 18 4 13 t292 busclk delay from procclk (all ratios) ---- 25 ---- 20 t293 -busy delay from -npbusy ---- 25 ---- 25 t294 -busy inactive from -xiow fall (output to port f0h) ---- 35 ---- 30 t295 -8042cs, -rttcs delay from procclk rise ---- 75 ---- 70 t296 procclk rise from cxin fall ---- 26 ---- 26 t297 procclk fall from cxin rise ---- 27* ---- 27* * 26ns maximum for 82c836a. table 12-22. miscellaneous parameters ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te296 procclk high symmetry t296-t297 ---- 3 ---- 2 te297 procclk low symmetry t297-t296 ---- 3 ---- 2 table 12-23. miscellaneous parameters ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t310 cxin cycle time 31 ---- 25 ---- t311 cxin low time 12 ---- 10 ---- t312 cxin high time 12 ---- 10 ---- t313 -npbusy active pulse width 30 ---- 30 ---- t314 -nperr fall after -busy fall 0 ---- 0 ---- t315 -nperr fall before -npbusy rise 30 ---- 25 ---- t316 -nperr active pulse width 35 ---- 30 ---- t317 -ready setup before procclk rise during coprocessor i/o cycles 19 ---- 12 ---- t318 -ready hold after procclk rise during coprocessor i/o cycles 4 ---- 4 ---- n ac characteristics 16- and 20mhz system characteristics 12-12 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
local bus access and cache the local bus access and cache timing specifications are shown in tables 12-24 through 12-27. table 12-24. local bus access and cache ---- output responses 16mhz 20mhz symbol parameters min. max. min. max. t342 -cas inactive from -ready rise 1 ---- 1 ---- t343 -cas fall from procclk fall during local memory write in early ready mode ---- * ---- * * not applicable to 82c836b. 22ns maximum for 82C836A-16. 20ns maximum for 82c836a-20. table 12-25. local bus access and cache ---- formula specifications 16mhz 20mhz symbol critical path formula min. max. min. max. te343 parity setup in early ready write t112-t343 ---- * ---- * * not applicable to 82c836b. 26ns maximum for 82C836A-16. 14ns maximum for 82c836a-20. table 12-26. local bus access and cache ---- input requirements 16mhz 20mhz symbol parameters min. max. min. max. t350 -lba setup before procclk rise 32 ---- 20 ---- t351 -lba hold after procclk rise 3 ---- 2 ---- t352 -ready setup before procclk rise during cache read hit or lba cycle 19 ---- 15 ---- t353 -ready hold after procclk rise during cache read hit or lba cycle 4 ---- 4 ---- system characteristics ac characteristics 16- and 20mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-13
standy refresh standby refresh timing specifications are shown in table 12-27. table 12-27. standby refreshoutput responses 16mhz 20mhz symbol parameters min. max. min. max. t370 -cas fall from 32khz rise or fall during standby refresh ---- 200 ---- 200 t371 ras0, 3 fall after -cas fall during standby refresh 12 ---- 12 ---- t372 -cas rise after ras1, 2 fall during standby refresh 47 2000 47 2000 t373 -ras low time during standby refresh 110 2000 110 2000 t374 -mwe rise before -ras fall in 32khz mode 15 ---- 15 ---- ac characteristics 25mhz the following parameters are for 25mhz operation in these system configurations: memory configurations up to 4 banks in mra mode only nonencoded ras; no buffers on cas or md lines 80ns dram, one wait state; or 60ns dram, zero wait state nonlatching buffer between sa-bus and cpu local address bus cache (peaksx) or non-cache. unless otherwise specified, the following timing parameters are defined under capacitive load of 50pf, vcc 4.75v to 5.25v, and temperature of 0 to 70 c. all the units discussed are in nanoseconds. also, these ac specifications are subject to change. formula specifications refer to the minimum or maximum result of a specified calculation involving other chip parameters. for any particular chip, formula specifications express a ?? tracking ?? relationship over temperature and voltage for the parameters involved in the formula. n ac characteristics 25mhz system characteristics 12-14 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
cpu to local memory tables 12-28 through12-30 provides the timing requirements for the cpu to access local memory. table 12-28. cpu to local memory ---- output responses symbol parameters min. max. t100 ras active from procclk rise ---- 23 t101 ras inactive from procclk rise ---- 26 t102 cas active from procclk rise ---- 23 t103 cas inactive from procclk rise ---- 27 t104 row address valid from procclk rise ---- 32* t105 row address hold from procclk rise 0 ---- t106 row address valid from a0-23 in ---- 50 t107 column address valid from procclk rise ---- 19 t108 column address hold from procclk rise 0 ---- t109 column address valid from a0-23 in ---- 47 t110 -mwe fall from -cas rise 0 36** t111 -mwe rise from procclk rise (c l = 30pf) ---- 26 t112 parl, parh valid from d0-15 write data in ---- 55 t113 -ready delay from procclk rise 4 31 * 30ns maximum for 82c836a. ** 58ns maximum for 82c836a. table 12-29. cpu to local memory ---- formula specifications symbol critical path formula max. te101 ras precharge t101-t100 19** te102 ras to cas delay t100-t102 9 te103 cas precharge t103-t102 7 te103a cas rise to ras fall t103-t100 6 te104 row address setup before ras t104-t100 11 te105 row address hold after ras t100-t105 5 te106 row address setup before ras t106-t100 28 te107 column address setup before cas t107-t102 6 te108 column address hold after cas t102-t108 2 te109 column address setup before cas t109-t102 25 te111 mwe rise before cas fall t111-t102 6* te112 write parity setup before cas t112-t102 10 * 13ns maximum for 82c836a. ** 5ns maximum for 82c836a. system characteristics ac characteristics 25mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-15
table 12-30. cpu to local memory ---- input requirements symbol parameters min. max. t120 parl, parh setup before procclk rise during read 7 ---- t121 parl, parh hold after procclk rise during read 5 ---- t122 d0-15 setup before procclk rise during read 7 ---- t123 d0-15 hold after procclk rise during read 5 ---- cpu to at-bus, on-board i/o, and rom tables 12-31 through 12-33 shows the cpu at bus, on-board i/o, and rom accesses. table 12-31. cpu to at-bus, on-board i/o, and rom ---- output responses symbol parameters min. max. t130 lomegcs delay from procclk rise ---- 35 t131 -na delay from procclk rise (c l = 25pf) ---- 15 t132 -ready delay from procclk rise 4 31 t133 ale rise from busclk low ---- 25 t134 ale fall from busclk high ---- 15 t135 command and -romcs active from busclk ---- 30 t136 command and -romcs inactive from busclk rise ---- 25 t137 moda0 delay from procclk rise ---- 30 t138 moda0 rise from busclk fall during bus convert ---- 20 t139 moda20 delay from a20 (if moda20 enabled) ---- 35 t140 moda20 delay from hold fall ---- 40 t141 sdirl, h delay from procclk rise ---- 50 t142 xd0-15 delay from procclk rise during write ---- 50 t143 xd0-15 turn-on delay from procclk rise 5 ---- t144 xd0-15 turn-off delay from procclk rise ---- 50 t145 xd0-15 delay from d0-15 during cpu write or master read ---- 30 t146 xd0-7 delay from d8-15 during cpu write (byte swap) ---- 70 t147 d0-15 delay from xd0-15 during cpu read or dma/master write ---- 25 t148 d8-15 delay from xd0-7 during cpu read (byte swap) or dma ---- 40 n ac characteristics 25mhz system characteristics 12-16 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-32. cpu to at bus and on-board i/o and rom ---- formula specifications symbol critical path formula max. te133 ale width t133-t134 10 te137 moda0 hold after command rise t136-t137 16 te139 memcs16 setup before ale fall t139-t134 15** te145 master read, access from cas t145+t102 38* te145a master read, access from column address t145+t107 34 * 36ns maximum for 82c836a. ** 20ns maximum for 82c836a. table 12-33. cpu to at-bus, on-board i/o, and rom ---- input requirements symbol parameters min. max. t160 -ads setup before procclk rise** 23 ---- t161 -ads hold after procclk rise** 4 ---- t162 a0-23 setup before procclk rise ? 39 ---- t163 a0-23 hold after procclk rise ? 4 ---- t164 -bhe setup before procclk rise ? 39 ---- t165 -bhe hold after procclk rise ? 4 ---- t166 -dc, w/-r and m/-io setup before procclk rise ? 39 ---- t167 -dc, w/-r and m/-io hold after procclk rise ? 4 ---- t168 iochrdy setup before busclk rise * 15 ---- t169 iochrdy hold after busclk rise * 15 ---- t170 -0ws setup before busclk fall * 10 ---- t171 -0ws hold after busclk fall * 20 ---- t173 -iocs16 hold after command inactive 0 ---- t174 -memcs16 setup before ale fall 30*** ---- t175 -memcs16 hold after ale fall 10 ---- t176 xd0-15 valid before read command rise 20 ---- t177 -iocs16 setup before busclk rise (first busclk rise after i/o command fall) 0 ---- ? these parameters are referenced to middle of t-state in which -ads changes from low to high (ts). ? referenced to end of ts. * nonrestrictive ** at start of ts. *** 25ns minimum for 82c836a. system characteristics ac characteristics 25mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-17
dma to at-bus, on-board i/o, and rom tables 12-34 through 12-36 shows the dma to at bus, on-board i/o, and rom accesses. table 12-34. 197dma to at-bus, on-board i/o, and rom ---- output responses symbol parameters min. max. t190 -dackn or -dacken delay from busclk rise ---- 46 t191 ale rise from hlda rise ---- 70 t192 dma address delay from busclk rise. note: dma address refers to a0-23, moda0, moda20, and -bhe ---- 35 t194 command fall from busclk rise ---- 40 t195 command rise from busclk rise ---- 40 t197 tc rise from busclk rise ---- 40 t198 tc fall from busclk rise ---- 35 t199 lomegcs delay from a16-23 ---- 35 t200 hold delay from procclk rise at start of t-state 5 25 t201 dsela, b delay from osc2 rise (mra mode) ---- 35 t202 dacka, b, c valid before dacken fall (mra mode) 0 ---- t203 dacka, b, c hold after dacken rise (mra mode) 0 ---- table 12-35. dma to at-bus, on-board i/o, and rom ---- formula specifications symbol critical path formula max. te194 command low time t194-t195 10 te195 command high time t195-t194 10 table 12-36. dma to at-bus, on-board i/o, and rom ---- input requirements symbol parameters min. max. t210 hlda setup before busclk rise ? 15 ---- t212 dreq setup before busclk rise ? 15 ---- t213 dreq hold after busclk rise ? 15 ---- t214 iochrdy setup before busclk rise ? 10 ---- t215 iochrdy hold after busclk rise ? 5 ---- ? these parameters are nonrestrictive. the signal may not be recognized until the subsequent clocking period if these parameters are violated. the parameter specifies only the condition needed to guarantee recognition of the signal on a particular clock edge. n ac characteristics 25mhz system characteristics 12-18 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
dma and at-bus master access to local memory the dma and at bus master access to local memory are shown in tables 12-37 through 12-39. table 12-37. dma and at-bus master access to local memory ---- output responses symbol parameters min. max. t230 -ras high from hlda rise ---- 50 t231 a0-23 and -bhe float from -master active ---- 60 t232 command float from -master active ---- 30 t233 -mwe rise from -xmemr fall ---- 40* t234 -mwe fall from -cas rise 2 60 t235 -ras inactive from -xmemr or -xmemw high ---- 42 t236 -cas inactive from -xmemr or -xmemw high ---- 50 t239 -ras active from xmemr or xmemw ---- 36 t240 a20 valid from moda20 during master access ---- 25 t241 a0 valid from moda0 during master ---- 19 t242 sdirl, h fall from -xmemw fall (master write) ---- 40 * 35ns maximum for 82c836a. table 12-38. dma and at-bus master access to local memory ---- formula specifications symbol critical path formula max. te230 ras precharge before refresh t230-t263-t265 27 te233 mwe rise before cas fall (read) t233-t102 18 te235 ras precharge, master t235-t239 16 te239 master read, access from ras t239+t145 51 te240 row address setup before ras t240-t239+t106 25 te242 master write, sdir fall t242+t147 65 table 12-39. dma and at-bus master access to local memory ---- input requirements symbol parameters min. max. t250 parl, parh setup before -xmemr rise during memory read 20 ---- t251 parl, parh hold after -xmemr rise during memory read 0 ---- system characteristics ac characteristics 25mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-19
refresh the refresh timing specifications are shown in tables 12-40 through 12-42 table 12-40. refresh ---- output responses symbol parameters min. max. t260 -refresh active from hlda ---- 71 t261 -refresh float from osc2 rise ---- 55 t262 refresh address valid from -refresh active. note: refresh address refers to moda0, a0-9 and ma0-9 ---- 45* t263 -xmemr active from osc2 rise ---- 55 t264 -xmemr inactive from osc2 rise ---- 50 t265 -ras0, -ras3 active from -xmemr fall ---- 30 t266 -ras0, -ras3 inactive from -xmemr rise ---- 25 t267 -ras1, -ras2 active from -xmemr fall ---- 70 t268 -ras1, -ras2 inactive from -xmemr rise ---- 70 t269 lomegcs delay from -refresh ---- 40 t270 -cas fall from hlda rise in cas-ras hlda refesh ** ---- t271 -refresh active from procclk in hidden refresh, or in hlda refresh in early ready mode following memory write ---- 50 t272 -xmemr fall from procclk in hidden refresh ---- 50 t273 -xmemr rise from procclk in hidden refresh ---- 50 * 40ns maximum for 82c836a. ** not applicable to 82c836b. 10ns minimum for 82c836a. table 12-41. refresh ---- formula specifications symbol critical path formula min. max. te260 ref to xmemr delay in hlda refresh t260-t263 ---- 16 te261 ref float after xmemr rise t261-t264 ---- 49 te270 cas precharge in cas-ras refresh t270-t103 * ---- te271 ref to xmemr in early ready mode t271-t263 ---- 16 te271a ref to xmemr delay in hidden refresh t271-t272 ---- 5** te272 xmemr low time in hidden refresh t272-t273 ---- 15*** te273 address hold after xmemr rise t273-t271 ---- 23 * not applicable for 82c836b. 9ns minimum for 82c836a. ** 1ns maximum for 82c836a. *** 4ns maximum for 836a. n ac characteristics 25mhz system characteristics 12-20 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-42. refresh ---- input requirements symbol parameters min. max. t280 iochrdy setup before osc2 rise ? 15 ---- t281 iochrdy hold after osc2 rise ? 5 ---- t282 -refresh setup before osc2 rise ? 20 ---- ? these parameters are nonrestrictive. the signal may not be recognized until the subsequent clock ing period if these parameters are violated. the parameter specifies only the conditions needed to guarantee re cognition of the signal on a particular clock edge. miscellaneous parameters miscellaneous timing specifications are shown in tables 12-43 through 12-45. table 12-43. miscellaneous parameters ---- output responses symbol parameters min. max. t290 xrst inactive from procclk rise (c l = 30pf) 4 12 t291 cpurst inactive from procclk rise (c l = 30pf) 4 12 t292 busclk delay from procclk (all ratios) ---- 20 t293 -busy delay from -npbusy ---- 25 t294 -busy inactive from -xiow fall (output to port f0h) ---- 30 t295 -8042cs, -rttcs delay from procclk rise ---- 70 t296 procclk rise from cxin fall ---- 26 t297 procclk fall from cxin rise ---- 27* * 26ns maximum for 82c836a. table 12-44. miscellaneous parameters ---- formula specifications symbol critical path formula min. max. te296 procclk high symmetry t296-t297 ---- 2 te297 procclk low symmetry t297-t296 ---- 2 system characteristics ac characteristics 25mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-21
table 12-45. miscellaneous parameters ---- input requirements symbol parameters min. max. t310 cxin cycle time 20 ---- t311 cxin low time 9 ---- t312 cxin high time 9 ---- t313 -npbusy active pulse width 30 ---- t314 -nperr fall after -busy fall 0 ---- t315 -nperr fall before -npbusy rise 25 ---- t316 -nperr active pulse width 30 ---- t317 -ready setup before procclk rise 9 ---- t318 -ready hold after procclk rise 4 ---- note: t317 and t318 apply to coprocessor accesses only. local bus access and cache the local bus access and cache timing specifications are shown in tables 12-46 through 12-48. table 12-46. local bus access and cache ---- output responses symbol parameters min. max. t342 -cas inactive from -ready rise 1 ---- t343 -cas fall from procclk fall during local memory write in early ready mode ---- * * not applicable for 82c836b. 20ns maximum for 82c836a. table 12-47. local bus access and cache ---- formula specifications symbol critical path formula max. te343 parity setup in early ready write t112-t343 * * not applicable for 82c836b. 14ns maximum for 82c836a. n ac characteristics 25mhz system characteristics 12-22 revision 3.0 p r e l i m i n a r y chips and technologies, inc.
table 12-48. local bus access and cache ---- input requirements symbol parameters min. max. t350 -lba setup before procclk rise 15 ---- t351 -lba hold after procclk rise 2 ---- t352 -ready setup before procclk rise 14 ---- t353 -ready hold after procclk rise 4 ---- standby refresh standby refresh timing specifications are shown in table 12-49. table 12-49. output responses ---- standby refresh symbol parameters min. max. t370 -cas fall from 32khz rise or fall ---- 200 t371 -ras0, 3 fall after -cas fall 12 ---- t372 -cas rise after -ras1, 2 fall 47 2000 t373 -ras low time 110 2000 t374 -mwe rise before -ras fall 15 ---- figure 12-1 shows the circuit load for the ac specifications of the 82c836. l c the specified test load. 0.06ns for each 1pf above output delays increase by figure 12-1. load circuit system characteristics ac characteristics 25mhz n chips and technologies, inc. p r e l i m i n a r y revision 3.0 12-23

section 14 mechanical specifications the 82c836 chipset is packaged in a 160-pin plastic flat pack. the dimensions are shown in figure 14-1. part lead pitch lead width lead length body footprint maximum height clearance package 82c836a 0.65 typ. 0.30 0.10 0.80 0.20 28.00 0.20 32.00 0.40 4.45 0.35/0.65 t 82c836b 0.65 typ. 0.34 0.09 0.80 0.20 28.00 0.20 32.00 0.30 4.00 0/0.25 s figure 14-1. package dimensions chips and technologies, inc. p r e l i m i n a r y revision 3.0 14-1
appendix a differences between 82c836a and 82c836b the 82c836b corrects various anomalies found in the 82c836a. refer to product alert 204.2/2-92 for details regarding these anomalies. the additional differences between 82c836a and 82c836b are as follows: for the 82c836a : icrs 61h and 62h are reserved. fast video mode is not supported. icr 46h bit 5 is reserved. there is no option to remap high rom addresses above 15mb to shadow ram below 1mb. icr 64h bit 7 is reserved. the 82c836a always ignores any cpu cycles that begin during cpu reset. the 82c836a does not support hidden refresh. during dram write operations in early ready mode, the 82c836a delays cas assertion by one half-cycle of procclk compared to the 82c836b. although this allows extra margin for write data and parity setup before cas falls, it also reduces the worst-case timing margin for write data hold after cas falls. the 82c836b greatly reduces the parity generation delay as well as improving cas timing to allow an increased worst-case margin for dram write data hold time. several differences in ac timing parameters are noted in section 12, system characteristics . chips and technologies, inc. p r e l i m i n a r y revision 3.0 a-1
chips and technologies, inc. 2950 zanker road san jose, california 95134 phone: 408-434-0600 fax: 408-894-2080 publication no.: ds96.3 stock no.: 010836-003 revision no.: 3.0 a

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